• ETRI Journal
• /
• v.35 no.3
• /
• pp.431-438
• /
• 2013

This paper presents a new realization of the implicit root-mean-square (RMS) detector, employing three second-generation current conveyors and MOS transistors. The proposed circuit can be applied in measuring the RMS value of complex, periodic signals, represented in the form of the Fourier series. To verify the theoretical analysis, circuit Simulation Program with Integrated Circuit Emphasis simulations and experiment results are included, showing agreement with the theory.

• 한국초전도학회:학술대회논문집
• /
• v.9
• /
• pp.13-15
• /
• 1999

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• Journal of the Korea Society for Simulation
• /
• v.3 no.1
• /
• pp.107-114
• /
• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.1
• /
• pp.48-59
• /
• 1992

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.384-388
• /
• 1986

This paper describes the design and fabrication of an integrated circuit that can detect the teletext signal included in a composite video signal. The circuit that is based on the comparatorlevel sampling method can detect a stable data signal even from an external circuit with large variation. It has been fabricated by the SST bipolar standard process. Its chip size is $2.5x3.78mm^2$.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1041-1044
• /
• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• ETRI Journal
• /
• v.8 no.1
• /
• pp.44-52
• /
• 1986

The main features of HILO-3 logic simulator are introduced. It is regarded as one of the most powerful logic simulator available now in electronic industry. The major functions and concepts are reviewed with some examples; circuit description using HDL (Hardware Description Language), waveform description using WDL (Waveform Description Language) and fault-free simulation for static RAM circuit. This program is expected to help the system designers, integrated circuit designers and test engineers.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.6
• /
• pp.992-997
• /
• 1987

This paper describes the design and fabrication of an integrated circuit that can separate the horizontal SYNC., vertical SYNC. and composite SYNC. signal included in a composite video signal. The circuit that is based on the comparator level samplign method can separate a stable SYNC. signal even from an external circuit with large variation. It has been fabrivated by the SST bipolar process. Its chip size is 1.5x1.5mm\ulcorner As a result, we succeeded in fabrication of IC which satisfied DC characteristics and SYNC. singal separator function.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.133-136
• /
• 2001

A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.

• Progress in Superconductivity
• /
• v.1 no.2
• /
• pp.81-84
• /
• 2000

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.