• Journal of Korean Elementary Science Education
• /
• v.24 no.5
• /
• pp.504-517
• /
• 2005

The purpose of this study was to develop an instrument for analysing elementary secondary school, and university science laboratory instructions. The categories of this analysis instrument were instituted through literature overviews and interactions with three researchers in a science classroom analyst team, a doctoral student, and eight master level students, who participated in the process of modification of the analysis instruments on the science laboratory instructions. The contents areas were divided into three categories: aims of laboratory activities, interactions, and scientific inquiry processes. Each category contains $2\~3$ items. So the instrument consisted of 20 subcategories. The validity of the this instrument was achieved through checking with 4 science education specialists.

• Journal of Korean Elementary Science Education
• /
• v.25 no.4
• /
• pp.454-464
• /
• 2006

The purpose of this study was to develop MBL(Microcomputer Based Laboratory) programs for sixth-grade elementary students in science laboratory instructions and to ascertain the effects of this program on academic achievement and science-related affective characteristics. In laboratory instructions, using the MBL was found to be effective in improving academic achievement for elementary students, especially in the domain of knowledge. In addition, it helped students to improve science-related affective characteristics. The experimental group showed higher levels, especially in the domains of cognition and interest. When our findings were analyzed in detail, the sub-domains that showed positive effects included 'cognition of science' in the domain of cognition, and interest toward science', 'interest toward science learning', 'interest toward science related activities', and 'anxiety for science' in the domain of interest. Male students exhibited improvement in the domain of cognition while female students showed improvement in the domain of interest. In conclusion, utilizing MBL programs as an experimental measurement in the real field of elementary science education can be said to be both positive and desirable.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.6
• /
• pp.124-132
• /
• 1985

The functional testing of microprocessor comes to be time - consuming task with the progress of technology of LSl/VLSl . In this paper, we present an efficient method to test instruction decoding function of MC 68000 that is the reason of complicated functional testing. This method is based on the analysis of operation word that is instruction dccoding information available to user with microprocessor's manual. Thc instruction is partitioned into representative instructions and party instructions. Then 332 minimum test instruction pairs are chosen from 69 basic instructions for detecting of instruction decoding function faults and test procedure for these is discussed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.6A
• /
• pp.405-413
• /
• 2003

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture to efficiently implement RS (Reed-Solomon) codecs, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various primitive polynomials by program, and thus, hardwired codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding rate of up to 228.1 Mbps on 130MHz DSP chips.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.1C
• /
• pp.12-18
• /
• 2008

This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

• Journal of the Korean Society of Clothing and Textiles
• /
• v.22 no.6
• /
• pp.716-724
• /
• 1998

The purpose of this study is to investigate the washing methods specified on care labels of blue jeans and to examine the appropriateness of the specification. In the study, the present condition of care labels on 100% cotton blue jeans was investigated and the consumers' washing methods of blue jeans were surveyed. Also, the shrinkage of blue jeans after washing was measured. The major results were as follows: 1. In spite of the fact that same materials of 100% cotton denim were used in all cases, washing signs on care labels showed very differently and the symbols of hand wash, using light duty detergent, no wring, drying in shade, and warm ironing with a covering cloth were demanding too high level of care for the protection of blue jeans. 2. Almost all consumers didn't follow instructions proposed on care labels because they didn't anticipate problem. In reality, most consumers washed blue jeans by machine in cold water with heavy duty detergent at standard course, dried under the sun, and didn't iron. The 40.8% of consumers didn't have problems even if they didn't follow instructions. Most problems happened after washing were shrinkage in length, but in shrinkage test after 15 times washings, it was found that there was no serious shrinkage problem. 3. For ideal care of blue jean, it is necessary for manufacturers to recognize the importance of care label and to stick correct appropriate care label. Also, consumers have to trust and follow instructions on care label.

• Journal of Korean Academy of Medicine & Therapy Science
• /
• v.10 no.2
• /
• pp.21-30
• /
• 2018

Objective: The purpose of this study was to investigate questions and instructions for internal feedback effects on functional recovery and task performance while chronic stroke patients practised task-specific training. Method: Twenty-four chronic stroke patients were randomly divided into two groups; when patients performed same tasks, one was treated using questions and the other using instructions for internal feedback Both lasted 30 minutes, 5 times a week for 8 weeks. Outcome measures included Erasmus MC Modifications to the Nottingham Sensory Assessment (EmNSA), Measurement Properties of the Motor Evaluation Scale for Upper Extremity in Stroke patients (MESUPES), Chedoke Arm and Hand Activity Inventory (CAHAI), Korean version of Modified Barthel Index (K-MBI). Results: There were no significant differences between the two groups in EmNSA and K-MBI(p>.05). But, in MESUPES and CAHAI, there was significant difference between the two groups(p<.05). Conclusion: In this study, questions for internal feedback during task-specific training are more effective in improving upper extremity motor function and task performance than instructions for internal feedback.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.1
• /
• pp.99-105
• /
• 2021

Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2009.11a
• /
• pp.241-242
• /
• 2009

As software is becoming increasing important to the human society, so does the effort to produce them is also increasing.. All of these efforts can be at risk when source code of the application is reverse engineered by the software pirate. Many attempts have been made to protect Intellectual Property Rights (IPR); one of the newest attempts to protect IPR is software watermarking. It is used to prove ownership right when IPR are violated, and also prevents the bandit from altering the code for his own use. In this paper we are presenting a new technique for software watermarking know as Dictionary Based Software Watermarking (DBSW). DBSW works by embedding dummy instructions in source code with the help of predefined mapping already available in the dictionary. These instructions are identical to the normal instructions of the program and are hard to identify or to extract from the watermarked program. With the help of DBSW we not only can stop source code alteration but can also identify the buyer how has distributed the pirated copy.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.4
• /
• pp.27-32
• /
• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.