• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.257-267
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• 2005

The real-time operating system(RTOS) simulator, one of the tools provided by RTOS development environment, allows users to develop and debug application programs even before the target hardware is ready. Thus, most of commercial RTOS development environments provide with RTOS simulator for the purpose. But they are implemented to simulate only functional aspects on a host system, so that it is not possible to estimate execution time of application programs on the target hardware. Since the real-time system has to complete program executions in predetermined time, the RTOS simulator that can estimate the execution time is yeW useful in the development phase. In this study, we develop a machine instruction-level RTOS simulator that is able to estimate execution time of application programs on a target hardware, and prove its functionality and accuracy by using test .programs.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1021-1030
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• 2010

In the sensor network, many tiny nodes construct Ad-Hoc network using wireless interface. As this type of system consists of thousands of nodes, managing each sensor node in real world after deploying them is very difficult. In order to install the sensor network successfully, it is necessary to verify its software using a simulator beforehand. In fact Sensor network simulators require high fidelity and timing accuracy to be used as a design, implementation, and evaluation tool of wireless sensor networks. Cycle-accurate, instruction-level simulation is the known solution for those purposes. In this paper, we developed an instruction-level sensor network simulator for Telos sensor node as named TeloSlM. It consists of MSP430 and CC2420. Recently, Telos is the most popular mote because MSP430 can consume the minimum energy in recent motes and CC2420 can support Zigbee. So that TeloSlM can provide the easy way for the developers to verify software. It is cycle-accurate in instruction-level simulator that is indispensable for OS and the specific functions and can simulate scalable sensor network at the same time. In addition, TeloSlM provides the GUI Tool to show result easily.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.45-53
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• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.6
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• pp.358-370
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• 2007

Software simulations have been widely used for the design and application development of a wireless sensor network that is an infrastructure of ubiquitous computing. In this study, we develop a sensor network simulator that can verify the behavior of sensor network applications, estimate execution time and power consumption, and simulate a large-scale sensor network. To implement the simulator, we use an instruction-level parallel discrete-event simulation method. Instruction-level simulation uses executable images loaded into a real sensor board as workload, such that it results in the high degree of details. Parallel simulation makes simulation of a large-scale sensor network possible by distributing workload into multiple computers. The simulator can predict the amount of power consumption based on operating time of modules in a sensor node and counting the number of executed instructions by kind. Also it can simulate ubiquitous applications with various scenarios and debug programs. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• ETRI Journal
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• v.30 no.1
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• pp.47-58
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• 2008

In sensor networks, analyzing power consumption before actual deployment is crucial for maximizing service lifetime. This paper proposes an instruction-level power estimator (IPEN) for sensor networks. IPEN is an accurate and fine grain power estimation tool, using an instruction-level simulator. It is independent of the operating system, so many different kinds of sensor node software can be simulated for estimation. We have developed the power model of a Micaz-compatible mote. The power consumption of the ATmega128L microcontroller is modeled with the base energy cost and the instruction overheads. The CC2420 communication component and other peripherals are modeled according to their operation states. The energy consumption estimation module profiles peripheral accesses and function calls while an application is running. IPEN has shown excellent power estimation accuracy, with less than 5% estimation error compared to real sensor network implementation. With IPEN's high precision instruction-level energy prediction, users can accurately estimate a sensor network's energy consumption and achieve fine-grained optimization of their software.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.55-58
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• 2000

To achieve high performance by exploiting instruction level parallelism(ILP) aggressively in superscalar processors, value prediction is used. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively it's data dependent instruction based on the predicted outcome. In this paper, the performance of a hybrid value prediction scheme with dynamic classification mechanism is measured and analyzed by using execution-driven simulator for SPECint95 benchmark set.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.11-23
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• 1995

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.457-466
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• 2007

IEC61131-3 is the standard of control languages in which special purpose controllers and motion controllers such as PLC can be programmed. IL(Instruction List), one of the standard languages, is in assembly level but has some high-level features. This paper describes a formal semantics of IL in operational style. Previous works on IL semantics do not include functions and function blocks, which is not so practical. We define IL semantics including functions and function blocks.