Journal of the Korea Society for Simulation (한국시뮬레이션학회논문지)

The Korea Society for Simulation (한국시뮬레이션학회)
권호 표지

Performance Improvement of ASIP Assembly Simulator Using Compiled Simulation Technique

컴파일방식 시뮬레이션 기법을 이용한 ASIP 어셈블리 시뮬레이터의 성능 향상

  • 김호영 (한국과학기술원 전자전산학과) ;
  • 김탁곤 (한국과학기술원 전자전산학과)
  • Published : 2003.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

Keywords

References

  1. Proc. of IEEE Workshop on VLSI Signal Processing Compiled simulation of programmable DSP Architectures V.Zivojnovic;S.Tjiang;H.Meyr
  2. Proc. of the Design Automation Conference(DAC) Generation of softweare tools from porcessor descriptions for hardware/software codesign M.Hartoog;J.Rowson;et al.
  3. Proc. Int. Conf. on Signal Processing Application and Technology Fast Simulation of the TITMS 320C54x DSP S.Pees;V.Zivojnovic;A.Ropers;H.Meyr
  4. Proceedings of European Design and Test Conference, Paris France Describing instruction set processors using nML A.Fauth;J.VanPraet;M.Freericks
  5. Proc. of the Conference on Design, Automation & Test in Europe EXPRESSION:A language for architecture expoloration through compiler/simulator retargetability A.Halambi;P.Grun;et al.
  6. Proc. DAC ISDL:An insturction set description language for retargetability G.Hadjiyiannis et al.
  7. Proceedings of the IEEE Workshop on VLSI Signal Processing LISA-machine description language and generic machine model for HW/SW co-design V.Zivojnovic;S.Pees;H.Meyr
  8. Proc. of the Asia & South Pacific Design Automation Conference(ASP-DAC0 Generation of Interpretive and Compild Instruction Set Simulators R.Leupers;J.Elste;B.Landwehr
  9. Proc. IEEE/ACM International Symposium on MediaBench:a tool for evaluating and synthesizing multimedia and communications systems C.Lee;M.Portkonjak;W.H.Mangione-Smith