Journal of the Korean Institute of Telematics and Electronics B (전자공학회논문지B)
- Volume 32B Issue 3
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- Pages.11-23
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- 1995
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- 1016-135X(pISSN)
Design of a Parallel Pipelined Processor Architecture
병렬 파이프라인 프로세서 아키덱처의 설계
Abstract
In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.
Keywords