• The Korean Journal of Emergency Medical Services
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• v.17 no.3
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• pp.139-147
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• 2013

Purpose: The purpose of the study is to confirm the effect of ACLS program using simulations and understanding self-efficacy, practice satisfaction, learning attitude, and interest in ACLS after theory classes and simulation-based practice. Methods: A non-equivalent simulation-based practice post test design was used. The participants were 28 paramedic students. The students participated in simulation-based practice for 3 weeks and conventional instruction class for 12 weeks. Results: The students showed higher level of self-efficacy(p=.043), practice satisfaction(p<.001) and learning attitude(p=.003) compared to the conventional lecture students. Conclusion: Level of self-efficacy after simulation-based practice for ACLS was higher than that of self-efficacy after conventional instruction classes. Level of practice satisfaction was also higher. Academic achievement after simulation-based practice was higher than that in conventional instruction classes.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.45-53
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• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.220-228
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• 2001

Simulation of an instruction set is essential to design and optimize new microprocessors, and to develop application programs. Though many simulation tools are widely used, their low-level description and simulation make users construct simulators difficult and spend a lot of time for simulation. We developed an automatic generator of instruction set simulators that perform register-transfer-level simulation. This automatic generator might be adaptable so as to be suitable for new modification or different conditions in designing microprocessors. In this paper, we describe a structure of automatic generation system and an implementation details.

• Radiation Oncology Journal
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• v.37 no.3
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• pp.201-206
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• 2019

Purpose: To observe the effectiveness of the practical instruction sheet and the educational video for left-sided breast treatment in a patient receiving deep inspiration breath hold (DIBH) technique. Two parameters, simulation time and patient satisfaction, were assessed through the questionnaire. Methods: Two different approaches, which were the instruction sheet and educational video, were combinedly used to assist patients during DIBH procedures. The guideline was assigned at least 1 week before the simulation date. On the simulation day, patients would fill the questionnaire regarding their satisfaction with the DIBH instruction. The questionnaire was categorized into five levels: extremely satisfied to dissatisfied, sequentially. The patients were divided into four groups: not DIBH technique, DIBH without instruction materials, the DIBH with instruction sheet or educational video, and DIBH with both of instruction sheet and educational video. Results: Total number of 112 cases of left-sided breast cancer were analyzed. The simulation time during DIBH procedure significantly reduced when patients followed the instruction. There was no significant difference in simulation time on the DIBH procedures between patient compliance via instruction sheet or educational video or even following both of them. The excellent level was found at 4.6 ± 0.1 and 4.5 ± 0.1, for patients coaching via instruction sheet as well as on the educational video, respectively. Conclusion: Patient coaching before simulation could potentially reduce the lengthy time in the simulation process for DIBH technique. Practicing the DIBH technique before treatment is strongly advised.

• ETRI Journal
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• v.30 no.1
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• pp.47-58
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• 2008

In sensor networks, analyzing power consumption before actual deployment is crucial for maximizing service lifetime. This paper proposes an instruction-level power estimator (IPEN) for sensor networks. IPEN is an accurate and fine grain power estimation tool, using an instruction-level simulator. It is independent of the operating system, so many different kinds of sensor node software can be simulated for estimation. We have developed the power model of a Micaz-compatible mote. The power consumption of the ATmega128L microcontroller is modeled with the base energy cost and the instruction overheads. The CC2420 communication component and other peripherals are modeled according to their operation states. The energy consumption estimation module profiles peripheral accesses and function calls while an application is running. IPEN has shown excellent power estimation accuracy, with less than 5% estimation error compared to real sensor network implementation. With IPEN's high precision instruction-level energy prediction, users can accurately estimate a sensor network's energy consumption and achieve fine-grained optimization of their software.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.6
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• pp.358-370
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• 2007

Software simulations have been widely used for the design and application development of a wireless sensor network that is an infrastructure of ubiquitous computing. In this study, we develop a sensor network simulator that can verify the behavior of sensor network applications, estimate execution time and power consumption, and simulate a large-scale sensor network. To implement the simulator, we use an instruction-level parallel discrete-event simulation method. Instruction-level simulation uses executable images loaded into a real sensor board as workload, such that it results in the high degree of details. Parallel simulation makes simulation of a large-scale sensor network possible by distributing workload into multiple computers. The simulator can predict the amount of power consumption based on operating time of modules in a sensor node and counting the number of executed instructions by kind. Also it can simulate ubiquitous applications with various scenarios and debug programs. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• 대한공업교육학회지
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• v.33 no.1
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• pp.149-168
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• 2008

The purpose of this study is to verify the effect of PSpice instruction on academic achievement in 'Combination logic circuit' unit of 'Digital Logic Circuit' in industrial high school. Three kinds of null hypotheses were formulated. Two classes of the third grade of C technical high school in Gyeong-buk were divided into experimental group and control group in order to verify null hypotheses. In the experimental design, 'Non-equivalent control group pretest-posttest' model was utilized. This experiment was conducted for six classes, the experimental group was applied to PSpice instruction method before the circuit traning while the control group was applied to traditional lecture oriented method before the circuit traning. Window SPSS 10.0 korean language version program was used for the data analysis and independent sample t-test was used to identify the average of each group. Significance level was set to .05 level. The results obtained in this study were as follows; First, PSpice instruction had not an effect on academic achievement according to a group type. However, these instruction had an effect on the following sub-domains; the psychomotor domain. Second, PSpice instruction had not an effect on academic achievement according to a studies level. However, these instruction for middle and low level students had an effect on the cognitive and psychomotor domain, and for middle level students had an effect on the affective domain. Third, PSpice instruction had not an effect on shortening of a training requirement. However, this instruction for low level students had an effect on shortening of a training requirement. The study results of simulation instruction was chiefly efficient in the psychomotor domain. We could know that simulation instruction is efficient as went to a low level students than an upper level students. Thus, We may make the study effectiveness in various instruction method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.10-21
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• 1997

In this paper, we propose multiple instruction issuable multi-streaming as a processor architecture for 3D graphics processor. Multistreaming can eliminate inteferences within concurrently executing instructions inthe pipelined processor to allow enough parallelism for parallel processing. Through cycle level simulation study, we show that the proposed architecture outperforms a conventional RISC processor, MIPS R3000 by three times with reasonable resource overheads. Multiple instruction issuable multistreaming processor will be a bood architecture for instruction processor when a large number of threads are guaranteed.