• Title/Summary/Keyword: input reduction

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Frequency weighted reduction using Lyapunov inequalities (Lyapunov 부등식을 이용한 주파수하중 차수축소)

  • 오도창;정은태;이상경
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.12-12
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    • 2000
  • This paper consider a new weighted model reduction using block diagonal solutions of Lyapunov inequalities. With the input and/or output weighting function, the stability of reduced order system is quaranteed and a priori error bound is proposed. to achieve this, after finding the solutions of two Lyapunov inequalities and balancing the full order system, we find the reduced order systems using the direct truncation and the singular perturbation approximation. The proposed method is compared with other existing methods using numerical example.

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A Method of Input Shaper Design Using Virtual Mode for Undamped Vibration Systems (가상모드를 이용한 비감쇠 진동계 입력성형기 설계 방법)

  • Hong, S.W.;Choi, H.S.;Seo, Y.G.;Park, S.W.
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.17 no.6
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    • pp.83-90
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    • 2008
  • Input shaping is an efficient tool to eliminate transient and residual vibration caused by motion of mechanical systems. However, the rise time of the systems tends to increase due to the presence of input shapers. This paper is concerned with the rise time reduction when using input shaping. To this end, this paper proposes an input shaper design method for an undamped single mode vibration system using a virtual mode, which is not an actual mode but reflected in the design process. The essence of the proposed method is to design a three-impulse input shaper as if a single mode system has two modes: one actual mode and one virtual mode. The natural frequency of the virtual mode is a design parameter to change the rise time of the system. This paper discusses the performance of the proposed input shapers by simulation.

A Study on the Microcontroller Input Port Reduction of IoT Equipments with Mixed Digital and Analog Inputs (디지털과 아날로그 입력이 혼용된 IoT 기기의 마이크로컨트롤러 입력포트 절감에 관한 연구)

  • Lee, Hyun-Chang
    • Journal of Convergence for Information Technology
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    • v.9 no.9
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    • pp.38-43
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    • 2019
  • In this paper, a method of inputting one analog input and two digital switch inputs by using one analog port of microcontroller embedded in IoT device was proposed. In this method, the upper limit and the lower limit of the input voltage range of the analog input port are determined, and the analog input voltage is input to this interval. The digital switches are configured to exceed the boundaries of the upper and lower limits, respectively. To verify the performance of the proposed method, an experimental circuit was constructed and tested using a microcontroller. As a result, all three inputs can be sensed using a single analog port, thus confirming that the three required input ports are reduced to one input port, ie, 33%.

Harmonic Reduction of Three Phase Multi-Pulse Converter Circuit without Input Transformer (입력 변압기 없는 3상 멀티-펄스 콘버터의 고조파 저감)

  • Park, Hyun-Chul;Kim, Yeong-Min;Hwang, Jong-Sun;Kim, Jong-Man
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.05b
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    • pp.128-131
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    • 2002
  • In this paper, a new method for reducing harmonic in input AC line currents of converter presents, which is the multi-pulse converter circuit without the input transformer. This system can reduce the harmonic like conventional 12-pulse converter. Both the bridge circuits are controlled with the shifted firing angle and connected 2 tap inter-phase reactor. Using 2 tap changing on inter-phase reactor, the input current is controlled with the different two values in order to make the input current waveform 12 pulses.

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REDUCTION OF VOLTAGE STRESS AND INPUT CURRENT HARMONIC DISTORTION IN SINGLE STAGE PFC CONVERTER BY SELECTIVE VARIABLE FREQUENCY CONTROL (선택적 주파수 변환방식에 의한 단상 역률보상회로의 캐패시터전압 및 입력전류 고조파왜곡의 감소)

  • Choi, Hang-Seok;Lee, Kyu-Chan;Cho, Bo-Hyung
    • Proceedings of the KIEE Conference
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    • 1997.07f
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    • pp.1999-2001
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    • 1997
  • The main two drawbacks of the Sin91e Stage PFC (SS-PFC) converters employing a DCM Boost PFC cell are relatively high voltage stress on the bulk capacitor and the input current harmonic distortion. The high voltage stress on bulk capacitor makes the SS-PFC converter impractical in a universal input application and the input current harmonic distortion lowers power factor. In this paper a selective variable frequency control that reduces the voltage stress on the bulk capacitor and the input current harmonic distortion is proposed. Computer simulation results of the proposed control method are presented.

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The Vibration Control of Flexible Manipulators using Adaptive Input Shaper (적응 입력다듬기를 이용한 유연한 조작기의 진동제어)

  • 신효필;정영무;강이석
    • Journal of Institute of Control, Robotics and Systems
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    • v.5 no.2
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    • pp.220-227
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    • 1999
  • The position control accuracy of a robot arm is significantly deteriorated when a long slender arm robot is operated at a high speed. In this case, the robot arm needs to be modeled as a flexible structure, not a rigid one, and its control system needs to be designed with its elastic modes taken into account. In this paper, the vibration control scheme of a one-link flexible manipulator using adaptive input shaper in conjunction with PID controller is presented. The robot consists of a flexible arm manufactured with a thin aluminium plate, an AC servo motor with a harmonic drive for speed reduction, an optical encoder and an accelerometer. On-line identification of the vibration mode is done using the pruned decimation-in-time FFT algorithm to estimate the parameter of the input shaper. Experimental results of the flexible manipulator with a PID controller and input shaper are provided to show the effectiveness of the advocated controllers.

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A Test Input Sequence for Test Time Reduction of $I_{DDQ}$ Testing

  • Ohnishi, Takahiro;Yotsuyanagi, Hiroyuki;Hashizume, Masaki;Tamesada, Takeomi
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.367-370
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    • 2000
  • It is shown that $I_{DDQ}$ testing is very useful for shipping fault-free CMOS ICs. However, test time of $I_{DDQ}$ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of $I_{DDQ}$ testing. At first, it is Shown that $I_{DDQ}$ test time Will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed. The feasibility is checked by some experiments.riments.

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Systolic Arrays for Lattice-Reduction-Aided MIMO Detection

  • Wang, Ni-Chun;Biglieri, Ezio;Yao, Kung
    • Journal of Communications and Networks
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    • v.13 no.5
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    • pp.481-493
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    • 2011
  • Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

A Study on the Active Noise Control System for Road Noise Reduction Implementation and Characterization of Directional and Non-directional Speaker (도로 소음 저감용 능동소음 제어시스템의 구현과 지향성 및 무지향성 스피커의 특성 고찰)

  • Moon, Hak-Ryong;Lim, You-Jin
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.62 no.4
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    • pp.192-197
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    • 2013
  • Road traffic noise barriers being used to reduce the noise, but the city surroundings inhibition, ecosystem disturbance, and it is difficult to maintain. Can enhance or complement the existing noise barrier performance, so that it is necessary to develop an electronic noise-reduction system In this paper, we proposed an electronic road noise reduction devices to reduce road noise for a DSP-based signal processing and analog signal input-output controller. In order to verify the control performance, we performed noise reduction experimentation of ANC by filtered-X LMS algorithm and traffic noise signal injection. The controller is equipped with noise reduction algorithms were tested on the characteristics of directional and omnidirectional speaker.

Vibratory Loads Reduction of a Coaxial Rotorcraft Using Individual Blade Control Scheme (개별 블레이드 제어(IBC) 기법을 이용한 동축반전 회전익기의 진동하중 억제에 관한 연구)

  • Hong, Seonghyun;You, Younghyun;Jung, Sung Nam;Kim, Do-Hyung
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.47 no.5
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    • pp.364-370
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    • 2019
  • In this paper, an individual blade control (IBC) methodology is applied to find the best input scenario for vibratory hub loads reduction of XH-59A co-axial rotorcraft in high speed flight. A comprehensive aeromechanics analysis code CAMRAD II is employed to analyze the aircraft. A parametric study is conducted for optimum IBC inputs leading to the maximum vibration reduction. Numerical results demonstrate that up to 50% reduction in the hub vibration index is obtained for an IBC input at 3/rev frequency with the amplitude and phase angle of 0.5 deg. and 300 deg., respectively. The upper rotor exhibits as much as 6% more vibration reduction as compared to that of the lower rotor due to a clean inflow characteristic of the rotor. It is found that further vibration reduction gain is reached for IBC inputs with advancing-side only control. The hub vibration becomes reduced by up to 17% in reference to that with full rotor disk control. It is noted that the additional gain is obtained with significantly less power input with the advancing-side only control.