• Journal of KIISE:Computer Systems and Theory
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• v.35 no.8
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• pp.378-384
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• 2008

Many embedded systems are supporting Java as their software platform via Java virtual machine. Java virtual machine manages memory automatically by providing automatic memory management, i.e. garbage collector. Because only scarce memory is available to embedded system, Java virtual machine should use small memory and manage it efficiently. This paper introduces two memory management techniques to exploit small memory in Java virtual machine which can execute multiple Java applications concurrently. First, compaction based garbage collection is introduced to overcome external fragmentation problem in presence of immovable memory area. Then garbage collector driven class unloading is introduced to reduce memory use of unnecessary loaded classes. We implemented these techniques in working embedded system and observed that they are very efficient, since more Java applications are able to be executed concurrently and memory use is also reduced with these techniques.

• The KIPS Transactions:PartD
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• v.10D no.2
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• pp.187-194
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• 2003

Main Memory storage system can increase the performance of the system by assigning enough slack time to real-time transactions. Due to its high response time of main memory devices, main memory resident data management systems have been used for location management of personal mobile clients to cope with urgent location related operations. In this paper we have developed a multi-threaded main memory storage system as a core component of real-time retrieval system to handle a huge amount of readers and writers of main memory resident data. The storage system is implemented as an embedded component which is working with the help of a disk resident database system. It uses multi-threaded executions and utilizes latches for its concurrency control rather than complex locking method. It only saves most recent data on main memory and data synchronization is done only when disk resident database asks for update transactions. The system controls the number of read threads and update threads to guarantee the minimum requirements of real-time retrievals.

• Anxiety and mood
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• v.18 no.1
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• pp.32-37
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• 2022

Objective : Impaired working memory has been known to play an important role in the pathophysiology of obsessive-compulsive disorder (OCD) with growing evidence. Delayed matching-to-sample task (DMST) is a working memory task which have an advantage in analyzing several different working memory processes in one task. However, most of the studies have failed to reveal the working memory impairment with the DMST. The aim of this study was to identify whether working memory deficit in OCD can be evaluated with the DMST. Methods : The participants included 20 OCD patients and 20 healthy volunteers. Working memory was evaluated with the DMST with two different working memory loads. Accuracy of response and mean response time were measured. Results : OCD patients showed a significantly longer reaction time and lower accuracy in DMST compared to healthy controls in the task with high working memory loads. Moreover, the difference in accuracy showed interaction with the working memory load. Conclusion : The present results indicate that working memory deficit in patients with OCD can be evaluated with the DMST. The findings also suggest that previous negative behavioral results using the DMST were from low working memory load of the task.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.71-77
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• 2009

OFDM(Orthogonal Frequency Division Multiplexing) signals sutler serious nonlinear distortion in the nonlinear HPA(High Power Amplifier) because of high PAPR(Peak Average Power Ratio). Nonlinear distortion can be improved by a pre-distorter, but this pre-distorter is insufficient when the PAPR is very high in an OPFDM system. In this paper, a DFT(Discrete Fourier Transform) transform technique is introduced for PAPR reduction. It is especially important to consider the memory effect of HPA for more precise predistortion. Therefore, in this paper, we consider two models, the TWTA(Traveling-Wave Tube Amplifier) model of Saleh without a memory effect and the HPA memory polynomial model that has a memory effect. We design a pre-distorter and an adaptive pre-distorter that uses the NLMS(Normalized Least Mean Square) algorithm for the compensation of this nonlinear distortion. Without the consideration of a memory effect, the system performance would be degraded, even if the pre-distorter is used for the compensation of the nonlinear distortion. From the simulation results, we can confirm that the proposed system shows an improvement in performance.

• ETRI Journal
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• v.34 no.5
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• pp.787-790
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• 2012

The objective of this research is to design a high-performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.1-10
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• 2016

Magnetic disks have been used for decades in auxiliary storage devices of computer systems. In recent years, the use of NAND flash memory, which is called SSD, is increased as auxiliary storage devices. However, NAND flash memory, unlike traditional magnetic disks, necessarily performs the erase operation before the write operation in order to overwrite data and this leads to degrade the system lifetime and performance of overall NAND flash memory system. Moreover, NAND flash memory has the lower endurance, compared to traditional magnetic disks. To overcome this problem, this paper proposes EPET (Enhanced Prediction and Elapsed Time) wear leveling technique, which is especially efficient to portable devices. EPET wear leveling uses the advantage of PET (Prediction of Elapsed Time) wear leveling and solves long-term system failure time problem. Moreover, EPET wear leveling further improves space efficiency. In our experiments, EPET wear leveling prolonged the first bad time up to 328.9% and prolonged the system lifetime up to 305.9%, compared to other techniques.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.1-8
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• 2011

NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way, victim and fully associative buffer with two or four sizes.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.9 no.3
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• pp.747-756
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• 2019

Students studying interpretation perform additional study and training in addition to regular class. In simultaneous interpreting and consecutive interpreting, interpreter should memorize speaker's announcement because of different language structure. To improve short-term memory, students perform memory training that requires a pair of students. Therefore, they can not perform self-learning, and therefore, efficiency of studying decreases. To resolve this problem, computer based short-term memory training system has been proposed. Student can perform self-learning by changing words in text to special character in the training system. However, efficiency of studying decreases because computer has low portability. Since the number of words is larger than the number of words to be switched into special character, learning difficulty decreases. To resolve this problem, smart device based short-term memory training system has been proposed. Student can perform smart device based training system without space constraints. Since the proposed training system increases the number of words to be changed into special character, learning difficulty increases. We implemented and evaluated the functionalities of the proposed training system.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.180-187
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• 2000

This paper presents the system of analyzing data in memory of TCMS. This system can show physical data in memory to text and graphic : format. To transfer data from TCMS to this system, a large number of system have used to memory IC card. the method of using memory IC card as a intermediation has many points at issue, that is a speed of transmitting data, life time of IC card and identity of train system each other. So this paper proposes that the method of wireless LAM be adopted by this system to improve the week point of previous method and other method to better the method of wireless LAN.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.