• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.1
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• pp.63-68
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• 2004

In this paper, we propose a method about the extraction of vehicle and tracking trajectory for moving vehicle tracking system in road. This system applied to the monitoring system of the traffic flow for ATMS(advanced traffic management system) of ITS(intelligent transport system). Also, this system can solve the problem of maintenance of loop sensor. And we detected vehicle using differential image analysis. Because of the road environment changes by real time. Therefore, the method to use background image is not suitable. And we used Kalman filter and innovation value and variable search area for vehicle tracking system. Previous method using fixed search area is sensitive to the moving trajectory and the speed of vehicle. Simulation results show that proposed method increases the possibility of traffic measurement more than fixed area traffic measurement system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.1-8
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• 2007

A wideband continuous-time sigma delta modulator for wireless application is implemented in 130nm CMOS. The SNR for small input signal is improved using a proposed adaptive quantizer which can effectively scale the quantization level. The modulator comprises a second-order loop filter for low power consumption, 4-bit quantizer and DAC for low jitter sensitivity and high linearity. Designed circuit achieves peak SNR of 51.36B with 10MHz signal Bandwidth and 320MHz sampling frequency dissipating 30mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Korean Journal of Materials Research
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• v.30 no.10
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• pp.495-501
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• 2020

The various sintered samples comprising of 72 wt% (Al₂O₃) : 28 wt% (SiO₂) based ceramics were fabricated using a colloidal processing route. The phase analysis of the ceramics was performed using an X-ray diffractometer (XRD) at room temperature confirming the presence of Al₂O₅Si and Al_5.33Si_0.67O_9.33. The surface morphology of the fracture surface of the different sintered samples having different sizes of grain distribution. The resistive and capacitive properties of the three different sintered samples at frequency sweep (1 kHz to 1 MHz). The contribution of grain and the non-Debye relaxation process is seen for various sintered samples in the Nyquist plot. The ferroelectric loop of the various sintered sample shows a slim shape giving rise to low remnant polarization. The excitation performance of the sample at a constant electric signal has been examined utilizing a designed electrical circuit. The above result suggests that the prepared lead-free ceramic can act as a base for designing of dielectric capacitors or resonators.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.40-46
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• 2005

A process variation compensation method called 'regulated drain detection' is proposed. This paper also shows the how this newly invented method is applied to a typical differential PLL. The proposed RDD(regulated drain detection) and its PLL application has been designed and tested in a $0.18{\mu}m$ 1-poly 3-metal plain digital process so that its stable performance and higher yield can be proven. The implemented PLL aimed to the operation range of 80MHz - 240MHz and the total die size is only $0.18{\mu}m$ including the internal loop filter. The tracking jitter characteristics is measured to less than 150 peak-to-peak under l.8V supply rail.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Journal of the Korean earth science society
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• v.36 no.7
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• pp.661-673
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• 2015

UBVI CCD photometry of the intermediate age open cluster NGC 7790 has been obtained using AZT-22 1.5 m telescope (f/7.74) at the Maidanak Astronomical Observatory in Uzbekistan. NGC 7790 contains three ${\delta}$ Cep variable stars including CEa Cas, CEb Cas, and CF Cas. PSF photometry was carried out using IRAF/DAOPHOT for all observations. The total number of stars observed both in V and I filter was 1008 and the limiting magnitude was $V{\approx}22$. To determine atmospheric extinction coefficients and photometric zero points, many blue and red standard stars as well as the standard stars in the celestial equator under various airmass were observed. Photometric data were transformed into the standard Johnson-Cousins' UBVI standard system. From the analysis of UBVI color-magnitude diagram and color-color diagram, the color excess in V and I filter [$E(B-V)=0.58{\pm}0.02$], the selective extinction ratio in V and I filter [$R_V{\equiv}A_V/E(B-V)=3.02{\pm}0.09$] and distance modulus ($V_0-M_V=12.65{\pm}0.10$) of the cluster were determined. The age of the cluster was estimated to be log $age=8.05{\pm}0.05$ [yr] based on the position of these three Cepheid variables in the color-magnitude diagram, the isochrone of the Geneva group ($Ekstr{\ddot{o}}m$ et al., 2012-Z=0.019), and the isochrone of the Padova group (Bressan et al., 2012-Z=0.014) were used to compare each other. Of them, the Geneva models that considered stellar rotation well described the position of ${\delta}$ Cepheid variables in the blue loop. Although they were well consistent with standard period-luminosity relation of ${\delta}$ Cepheid variables, three Cepheid variables in NGC 7790 were, on average, brighter by about 0.5 mag than the absolute magnitude estimated from the mean period-luminosity relation at a given period.