• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.838-841
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• 2005

DNA Chip is able to show DNA-Data that includes diseases of sample to User by using complementary characters of DNA. So this paper studied Neural Network algorithm for Image data processing of DNA-chip. DNA chip outputs image data of colors and intensities of lights when some sample DNA is putted on DNA-chip, and we can classify pattern of these image data on user pc environment through artificial neural network and some of image processing algorithms. Ultimate aim is developing of pattern classifying algorithm, simulating this algorithm and so getting information of one's diseases through applying this algorithm. Namely, this paper study artificial neural network algorithm for classifying pattern of image data that is obtained from DNA-chip. And, by using histogram, gradient edge, ANN and learning algorithm, we can analyze and classifying pattern of this DNA-chip image data. so we are able to monitor, and simulating this algorithm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.203-211
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• 1996

This paper describes CAD tools for the construction of image database in IC chip analysis CAD system. For IC chip analysis by high-resolution microscopy, the image database is essential to manage more than several thousand images. But manual database construction is error-prone and time-consuming. In order to solve this problem, we develop a set of CAD toos that include image grabber to capture chip images, image editor to make the whole chip image database from the grabbed images, and image divider to reconstruct the database that consists of evenly overlapped images for efficient region search. we also develop an interactive pattern matching method for user-friendly image editing, and a heuristic region search method for fast image division. The tools are developed with a high-performance graphic hardware with JPEG image comparession chip to process the huge color image data. The tools are under the field test and experimental resutls show that the database construction time can be redcued in 1/3 compared to manual database construction.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• The Research Journal of the Costume Culture
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• v.20 no.6
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• pp.869-882
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• 2012

The purpose of this study is to obtain the patent for extracting the color map and color chip from the color image source and to develop color image map for fashion design. For this study, fashion image maps were produced from 210 pictures with Adobe Photoshop CS2 program targeting 200 university students from 2004 to 2006. The procedures for extracting the color map and color chip included providing the color image, the filtering phase, the segmentation phase, the extraction phrase, and the arrangement phase. Based on the results of this study, patent application was made to KIPO(Korean Intellectual Property Office) for this invention. The following effects can be expected from the standpoint of design based on the case study. First, it is a straight forward procedure to extract a color chip and color map from a color image. Second, it can be applied to various art works based on the recombination of colors as representative colors can be extracted from the related color image that combines a variety of colors. Third, desired colors can be selected based on the taste cluster classification or sensibility axis of design by extracting the representative color from the color image.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.89-110
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• 2005

A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.29-33
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• 2002

In order to utilize remote sensed images widely, it is necessary to correct geometrically. Traditional approaches to geometric correction require substantial human operations. Such substantial human operations make geometric correction a laborious and tedious process. In this paper, We introduce concept of GCP(Ground Control Point) Chip and generate a GCP Chip for automatic geometric correction. GCP Chip is small image patch which has a GCP in reference coordinate image. GCP Chip will be used to match new images in geometric correction. We generated GCP chip using Landsat-7 ETM+ panchromatic band image in this study. Henceforth this result will support automatic process in geometric correction.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.811-815
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• 1990

This paper describes the method on image acquisition and image processing in the turning process. The formation of discontinuous chips during high-speed oblique cutting without lubricant was observed by means of video camera recorder and stroboscope. The image processing technique for chip flow is described and the results are presented for variable feeds. It is concluded that experimental values of chip flow angle are similar to theoretical values of Stabler's rule.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• Journal of Information Processing Systems
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• v.2 no.3 s.4
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• pp.189-193
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• 2006

In this study we propose an automatic reading system for diagnostic DNA chips. We define a general specification for an automatic reading system and propose a possible implementation method. The proposed system performs the whole reading process automatically without any user intervention, covering image acquisition, image analysis, and report generation. We applied the system for the automatic report generation of a commercialized DNA chip for cervical cancer detection. The fluorescence image of the hybridization result was acquired with a $GenePix^{TM}$ scanner using its library running in HTML pages. The processing of the acquired image and the report generation were executed by a component object module programmed with Microsoft Visual C++ 6.0. To generate the report document, we made an HWP 2002 document template with marker strings that were supposed to be searched and replaced with the corresponding information such as patient information and diagnosis results. The proposed system generates the report document by reading the template and changing the marker strings with the resultant contents. The system is expected to facilitate the usage of a diagnostic DNA chip for mass screening by the automation of a conventional manual reading process, shortening its processing time, and quantifying the reading criteria.