• Title/Summary/Keyword: hysteresis loop

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The Structural and electrical Properties of $BaTiO_3$ Thin Films Deposited on Si/MgO Substrates (Si/MgO 기판에 증착된 BaTiO$_3$ 박막의 구조 및 전기적 특성)

  • 홍경진;김태성
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.12
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    • pp.1108-1114
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    • 1998
  • $BaTiO_3$ thin films preferred c-axis orientation for the potential application of ferroelectric memory devices were deposited on silicon substrates(100) by RF sputtering and annealed at 800 and 900[$^{\circ}C$] in air. The BT(100)/BT(110) peak ratio of the sputtered sample was decreased with post-annealing in air. According to increasing with annealing temperature and time, the peak ratio of BT(100)/BT(110) was decreased and the surface density of thin film was high. Dielectric characteristics of $BaTiO_3$ thin film was measured as a function of annealing temperature and frequency. The dielectric constants were increased with annealing and decreased with frequency by space charge polarization and dipole polarization below 600[kHz]. The remanent polarization and coercive field in P-E hysteresis loop of $BaTiO_3$thin film were increased with the annealing temperature in air. The remanent polarization and coercive filed annealed at 800[$^{\circ}C$] for 1hr were 1.2[$\mu$C/$cm^2$] and 200[kV/cm]

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Ferroelectric and leakage current characteristics of Pt/SBT/Pt capacitors with post annealing process (후속 열처리에 따른 Pt/SBT/Pt 캐패시터의 강유전 특성과 누설전류 특성)

  • 권용욱;박주동;연대중;오태성
    • Journal of the Korean Vacuum Society
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    • v.8 no.3A
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    • pp.238-244
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    • 1999
  • Pt/SBT/Pt capacitors were fabricated using the MOD-derived $SrBi_{2x}Ta_2O_9$ (SBT) films and their ferroelectic and leakage current characteristics were investigated with post annealing at 400~$800^{\circ}C$. Although the MOD-derived SBT film exhibited the hysteresis loop typical for the leaky film, the well-saturated ferroelectric hysteresis loop could be obtained by post annealing the Pt/SBT/Pt capacitors at $550^{\circ}C$~$800^{\circ}C$. The remanent polarization $2P_r$ of the SBT film exhibited a maximum value of 9.72$\mu\textrm{cm}^2$ with post annealing at $600^{\circ}C$, and then decreased with increasing the post annealing temperature above $600^{\circ}C$. The MOD-derived SBT films exhibited the high leakage current density of ~$10^{-3} \textrm{A/cm}^2$ at 75kV/cm. With post annealing the Pt/SBT/Pt capacitor at 600~$800^{\circ}C$, however, the leakage current density decreased remarkably to less than $10^{-6}\textrm{A/cm}^2$ at 75kV/cm.

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Structural health monitoring for pinching structures via hysteretic mechanics models

  • Rabiepour, Mohammad;Zhou, Cong;Chase, James G.;Rodgers, Geoffrey W.;Xu, Chao
    • Structural Engineering and Mechanics
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    • v.82 no.2
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    • pp.245-258
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    • 2022
  • Many Structural Health Monitoring (SHM) methods have been proposed for structural damage diagnosis and prognosis. However, SHM for pinched hysteretic structures can be problematic due to the high level of nonlinearity. The model-free hysteresis loop analysis (HLA) has displayed notable robustness and accuracy in identifying damage for full-scaled and scaled test buildings. In this paper, the performance of HLA is compared with seven other SHM methods in identifying lateral elastic stiffness for a six-story numerical building with highly nonlinear pinching behavior. Two successive earthquakes are employed to compare the accuracy and consistency of methods within and between events. Robustness is assessed across sampling rates 50-1000 Hz in noise-free condition and then assessed with 10% root mean square (RMS) noise added to responses at 250 Hz sampling rate. Results confirm HLA is the most robust method to sampling rate and noise. HLA preserves high accuracy even when the sampling rate drops to 50 Hz, where the performance of other methods deteriorates considerably. In noisy conditions, the maximum absolute estimation error is less than 4% for HLA. The overall results show HLA has high robustness and accuracy for an extremely nonlinear, but realistic case compared to a range of leading and recent model-based and model-free methods.

Optimized Low-Switching-Loss PWM and Neutral-Point Balance Control Strategy of Three-Level NPC Inverters

  • Xu, Shi-Zhou;Wang, Chun-Jie;Han, Tian-Cheng;Li, Xue-Ping;Zhu, Xiang-Yu
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.702-713
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    • 2018
  • Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

Exchange bias in NiFe/FeMn/NiFe multilayers

  • Sankaranarayanan, V.K.;Lee, Y.W.;Shalyguina, E.E.;Kim, C.G.;kim, C.O.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05a
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    • pp.55-58
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    • 2003
  • FeMn based spin valves often consist of a NiFe/FeMn/NiFe trilayer structure. We have investigated the evolution of exchange bias at the bottom and top interfaces in the NiFe(5nm)/FeMn(x)/NiFe(5nm) trilayer structure as a function of FeMn thickness in the range 3 nm to 30 nm. The XRD results indicate (111) textured growth for NiFe and FeMn layers. The magnetization studies using VSM show two hysteresis loops corresponding to the bottom NiFe seed layer and top NiFe layers with greater bias for the bottom NiFe layer, for FeMn thickness equal to and above 5 nm. The larger exchange bias for the bottom seed layer is confirmed by the surface sensitive MOKE hysteresis loop measurements which show gradual weakening of the MOKE hysteresis loop for the bottom NiFe layer with increasing FeMn thickness. The observed large exchange bias in a spin valve structure is usually attributed to the pinning NiFe layer on top of the FeMn layer, even when a NiFe seed layer of a few nm thickness is present, whereas, in reality it may be arising from the bottom seed layer, as shown by the present study.

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Motion Control of the Precise Stage using Piezoelectric Actuator (압전소자를 이용한 정밀 스테이지의 운동제어)

  • Kim, In-Soo;Kim, Yeung-Shik;Hwang, Yun-Sik
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.10 no.4
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    • pp.102-108
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    • 2011
  • LQG/LTR control scheme is applied to the two axes stage using piezoelectric actuator for tracking reference input and suppressing hysteresis effect in this paper. The plant is combined with an integrator to improve the tracking ability. LQG/LTR controller is designed by making desirable target filter loop remove all poles except for an integrator included in new design plant model and loop transfer recovery. Decoupler in the shape of FIR filter is added to remove the coupling effect between the two axes motion and so feedback control loop is designed independently for the each axis motion.

Effect of control route on the unstart/restart characteristics of an over-under TBCC inlet

  • Li, Nan;Chang, Juntao;Tang, Jingfeng;Yu, Daren;Bao, Wen;Song, Yanping
    • Advances in aircraft and spacecraft science
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    • v.5 no.4
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    • pp.431-444
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    • 2018
  • Numerical simulations have been conducted to study the unstart/restart characteristics of an over-under turbine-based combined-cycle propulsion system (TBCC) inlet during the inlet transition phase. A dual-solution area exists according to the Kantrowitz theory, in which the inlet states may be different even with the same input parameters. The entire transition process was divided into five stages and the unstart/restart hysteresis loop for each stage was also obtained. These loops construct a hysteresis surface which separates the operating space of the engine into three parts: in which a) inlet can maintain a started state; b) inlet keeps an unstarted state; c) inlet state depends on its initial state. During the transition, the operation of the engine follows a certain order with different backpressures and splitter angles, namely control route, which may result in disparate inlet states. Nine control routes with different backpressures and transition stages were designed to illuminate the route-dependent behavior of the inlet. The control routes operating towards the unstart boundary can make the inlet transit from a started state into an unstarted one. But operating backward the same route cannot make the inlet restart, additional effort should be made.

Compensation algorithm of a voltage transformer considering hysteresis characteristics (히스테리시스 특성을 고려한 전압 변성기 오차 보상 알고리즘)

  • Kang, Yong-Cheol;Zheng, Tai-Ying;Park, Jong-Min;Jang, Sung-Il;Kim, Yong-Guen
    • Proceedings of the KIEE Conference
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    • 2007.11b
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    • pp.12-14
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    • 2007
  • A voltage transformer (VT) is used to transform a high voltage into a low voltage as an input for a metering device or a protection relay. VTs use an iron core which maximizes the flux linkage. The primary current of the VT has non-fundamental components caused by the hysteresis characteristics of the iron core. It causes a voltage drop in the winding impedances resulting in the error of the VT. This paper describes a compensation algorithm for the VT. The proposed algorithm can compensate the secondary voltage of VT by calculating the primary current from the exciting current of the hysteresis loop in the voltage transformer. In this paper, the exciting branch was divided into a non-linear core loss resistor and a non-linear magnetizing inductor. The performance of the proposed algorithm was validated under various conditions using EMTP generated data. Test results show that the proposed compensation algorithm can improve the accuracy of the VT significantly.

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Identification of the Jiles-Atherton Model Parameters Using Simulated Annealing Method

  • Bai, Baodong;Wang, Jiayin
    • Journal of international Conference on Electrical Machines and Systems
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    • v.1 no.2
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    • pp.18-22
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    • 2012
  • This paper presents a method and the experimental measurement system for the determination of Jiles-Atherton model parameters of the 30ZH120 electrical steel sheet. The paper utilizes Epstein Square devices to proceed with the experiment and measurement on a group of hysteresis loops of some certain transformers which use the 30ZH120 electrical steel sheet under two different lap ways. The approach relies on the simulated annealing optimization method in order to minimize the error between the measured and modeled hysteresis curves and yield the best five Jiles-Atherton model parameters. A convenient program, based on the Simulink platform, that can identify the J-A model parameters automatically from the experimental saturated hysteresis loop which is used to model the nonlinear characteristics of the electrical steel sheet, is developed. Research shows that the simulated annealing optimization method gets satisfactory results.

A Circuit Simulation Model of Ferroelectric Capacitors and its AHDL Implementation (강유전체 캐패시터의 회로 시뮬레이션 모델과 이의AHDL 구현)

  • Kim, Shi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.10
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    • pp.25-32
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    • 2000
  • We provided a model for accurately computing the Hysteresis characteristics of the ferrelectric thin film capacitors. This model is developed form the semi-empirical ferroelectric model based on the double well harmonic oscillator. We have seen that this model is consistent with physical analysis using the Preisach's hysteresis distribution. This model includes the parameters representing the slope of changing Hysteresis curves and the imprint of ferroelectric capacitors. Besides, we showed that this model could predict accurate sub-hystersis loop by the turning points when the polarities of applied voltage were changed before saturation. The simulation and measurement result showed that this model is well applicable to both PZT and SBT materials. This model has been described by AHDL and successfully implemented into Spectre simulator to provide circuit design environment of commercial CAD tools such as Cadence software.

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