• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.61-70
• /
• 1996

In this paper, we find the values of near-end crosstalk coefficient in striplines of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, and define calcualtion errors in an analytic method and define the application range, and simualte near-end crosstalk coefficients of the FCT (fast CMOS TTL) in complicated striplines by HSPICE and analyze near-en crosstalk coefficients in relation to dielectric thickness and trace spaces of striplines. As a result, we analyze coupling structure of the near-end crosstalk in the coplicated sstriplines that are impedance matched and define a coupling formula of near-end crosstalk coefficients in general complicated striplines. Especially, it is approximated in the layout grade rule.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.61-67
• /
• 2006

We developed a constant current source which is insensitive to threshold voltage variation caused by irregular grain boundary distribution in polycrystalline silicon. The proposed current source has superior saturation characteristics over wide range of input voltages as well as small current error compared to the previously reported Vth compensated sources. We measured the circuit performance and error in current due to parameter variation by using HSPICE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.669-672
• /
• 2003

With the advances on wireless internet technology, many research on minimization of wireless LAN is on the progress. To apply passive components in MCM, characteristic analysis of passive components is essential. In this paper, three square spiral inductors were modeled by HSPICE using PEEC (Partial Element Equivalent Circuit) method. Afterwards, Monte-Carlo analysis was performed to evaluate the optimized parameters. This work will give an idea on PEEC modeling of spiral inductor, and enable researchers with predictive data before large scale manufacturing.

• The Journal of the Acoustical Society of Korea
• /
• v.19 no.1
• /
• pp.84-88
• /
• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of two fully differential transconductors and lowers supply voltage down to VT+2VDS,sat+VDS,triode. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25㎛ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7VP-P.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.6
• /
• pp.891-896
• /
• 2002

In this paper, a new voltage-controlled tunable integrator for low-voltage applications is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transcon-ductance is increased than that of the conventional element. And then these results are verified by the $0.25{\mu}m$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42dB and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.10C
• /
• pp.1019-1024
• /
• 2007

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.1985-1991
• /
• 1999

In this paper, complete and general two-port lumped Spice-network model is developed for a lossy transmission line. This model is realized as a Spice subcircuit, by means of standard lumped network elements and mathematical functions. It is used as a component in the time-domain simulation of a high-speed data transmission line such as IMI(Inter Module Interface) data path in HANbit ACE 64 ATM switching system. The only required Spice network elements are resistance and frequency-dependent controlled-voltage sources. Such frequency-dependent sources are realized by utilizing the standard Hspice mathematical functions FREQ, DELAY, and POLY.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.4
• /
• pp.20-29
• /
• 1998

In this paper, we find the values of near-end crosstalk coefficients in dual-offset stripline of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, define calculation errors inananlytic method and the application range, simulate near-end crosstalk coefficients of the FCT(Fast CMOS TTL) in complicated dual-offset stripline by HSPICE and analyze near-end crosstalk and far-end crosstalk coefficients in dual-offset stripline. So, we analyze coupling structure of the near-end crosstalk and far-end crosstalk in the complicated dual-offset striplines that are 1[pF] capacitors termainated, and define a coupling formula of near-end crosstalk and far-end crosstalk coefficients dual-offset striplines.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.691-693
• /
• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.697-699
• /
• 2017

A novel structure of phase locked loop (PLL) which has small size with D Flip-Flop and sub charge pump has been proposed. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.