• Laser Solutions
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• v.8 no.3
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• pp.21-26
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• 2005

A bonding process between tape-carrier package and a glass panel with anisotropic conductive film (ACF) has been investigated by making use of high power diode laser as a heat source for cure. The results from modeling of process and from optical properties of layers showed that heat absorbed from polyimide film surface and ACF layer is dominant source of curing during laser illumination. Laser ACF bonding has better bonding quality than conventional bonding in view of peel strength, flatness, pressure unbalance and processing time. New ACF bonding processes by making use of high power diode laser are proposed.

• 전기의세계
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• v.39 no.12
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• pp.63-67
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• 1990

MOSFET의 드레인 불순물 농도 분포는 hot carrier효과 및 드레인 누설전류 특성에서 중요한 요소가 된다. 특히 MOSFET의 게이트 아래 부분의 수평 농도는 게이트 전압에 의한 누설전류 특성에 큰 영향을 주는 것으로 알려져 있다.[1][2]. 보통의 수직농도분포는 SIMS기법, ARS 방법등을 이용하여 측정이 가능하다. 그러나, 수평 불순물 농도분포는 실험적으로 구하는 방법이 없었고 보통 이차원 공정 시뮬레이션(MINIMOS, SUPRA등)을 통하여 산출하였다. 최근 드레인의 수평 불순물 농도분포를 게이트와 드레인 사이의 용량 측정에 의해 구하는 방법이 제시되었다[3]. 이방법에서는 농도가 높은 경우에는 수평접합깊이를 절대적인 값으로 구하지 못하였다. 본 논문에서는 게이트-드레인간 용량 측정에 의해 수평접합깊이를 구하고 그 농도분포를 추출하는 방법을 제시하고, ASR방법에 의해 측정된 수직 불순물 농도분포와 비교하고 검토한다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.129.2-129.2
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• 2011

본 연구에서는 a-Si:H/c-si 구조의 이종접합 태양전지의 p a-Si:H 에미터 층의 박막 조건에 따라 태양전지 특성을 연구하였다. p, n-layer는 PECVD (Plasma-enhanced chemical vapor deposition) i-layer는 HWCVD(Hot wire chemical vapor deposition), ITO는 RF 마그네트론 스퍼터링법으로 제작하였다. p-layer의 도핑 농도, 기판 증착 온도, 증착 높낮이에 따라 특성을 비교 분석 하였다. QSSPC로 minority carrier life time, 자외 가시선 분광분석 장치로 투과 반사도를, Ellipsometer로 흡수 계수, 두께, FTIR로 막의 구성요소 등의 변화를 조사하여 개선된 p a-Si:H의 특성이 이종접합 태양전지에서 효율향상에 영향을 주는지 Photo IV와 EQE를 통하여 조사하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1301-1304
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• 2007

We have investigated degradation of short channel n-type poly-Si TFTs with LDD under high gate and drain voltage stress due to self-heating. We have found that the threshold voltage of short channel TFT is shifted to negative direction on the selfheating stress, whereas the threshold voltage of long channel is moved to positive direction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.141-144
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• 1998

The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

• Electrical & Electronic Materials
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• v.11 no.10
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• pp.94-99
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• 1998

Suitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higherpermittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and hot carrier effect measurements were done on 190 layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide (TTIP). Measurements of the high and low frequency capacitance indicate that virtually no interface state are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.19.2-19.2
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• 2011

ZnO nanowires have been fabricated by vapor-liquid-solidification with hot-walled pulsed laser deposition method. The diameter of ZnO nanowire has been systematically controlled simply by changing the thickness of Au catalyst. Field effect transistors with different diameter have been fabricated by using photolithography and e-beam lithography. The threshold voltage of ZnO nanowire FET showed enhanced mode and depleted mode depending on the diameter of ZnO nanowires. This is mainly due to the change of the carrier concentration depending on the size of nanowires. We have fabricated ZnO nanowire inverters using nanowire FETs. This simple method to fabricate ZnO nano-inverter will be useful to open the possibility of ZnO nanoelectronic applications.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.271-275
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• 1997

We have successfully grown Cl-doped ZnSe epitaxial layers on GaAs(100) sub-strates by HWE using $ZnCl_2$ as a doping source. The Cl-doped ZnSe layers showed mirrorlike morphology and good crystallinity. It has been found that the layer exhibited an n-type conduction with low resistivity. The carrier concentration is, obtained about $10^{16}\textrm {cm}^{-3}$, where a resistivity reached 10 $\Omega \textrm {cm}$. The layer with an appropriate doping level exhibited blue photoluminescence at room temperature. The strong blue PL was obtained at the hall mobility of $100^2\textrm {cm}$/Vㆍsec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.667-674
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• 2005

In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1442-1444
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• 2001

A new low-temperature poly-Si TFT employing a counter-doped lateral body terminal is proposed and fabricated, in order to enhance the stability of poly-Si TFT driving circuits. The LBT structure effectively suppresses the kink effect by collecting the counter-polarity carriers and suppresses the hot carrier effect by reducing the peak lateral field at the drain junction. The proposed device is immune to dynamic stress, so that it is suitable for low voltage and high speed driving circuits of AMLCD.