• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.

• Journal of Korea Multimedia Society
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• v.16 no.8
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• pp.954-961
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• 2013

To enhance the efficiency of network, content-centric networking (CCN), one of future Internet architectures, allows network nodes to temporally cache transmitted contents and then to directly respond to request messages which are relevant to previously cached contents. Also, since CCN uses a hierarchical content-name, not a host identity like source/destination IP address, for request/response packet routing and CCN request message does not include requester's information for privacy protection, contents-providers/ network nodes can not identify practical requesters sending request messages. So to send back relevant contents, network nodes in CCN records both a request message and its incoming interfaces on Pending Interest Table (PIT). Then the devices refer PIT to return back a response message. If PIT is exhausted, the device can not normally handle request/response messages anymore. Hence, it is needed to detect/react attack to exhaust PIT. Hence, in this paper, we propose improved detection/reaction schemes against attacks to exhaust PIT. In practice, for fine-grained control, this proposal is applied to each incoming interface. Also, we propose the message framework to control attack traffic and evaluate the performance of our proposal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1449-1454
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• 2015

Virtualization lacks capabilities for enabling the application to scale efficiently because of new applications components which are raised to be configured on demand. In this paper, we propose an architecture that affords mobile app based on nomadic smartphone using not only mobile cloud computing-cloudlet architecture but also a dedicated platform that relies on using virtual private mobile networks to provide reliable connectivity through LTE(Long Term Evolution) wireless communication. The design architecture lies with how the cloudlet host discovers service and sends out the cloudlet IP and port while locating the user mobile device. We demonstrate the effectiveness of the proposed architecture by implementing an android application responsible of real time analysis by using a vehicle to applications smartphone interface approach that considers the smartphone to act as a remote users which passes driver inputs and delivers outputs from external applications.

• Journal of Korea Multimedia Society
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• v.8 no.11
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• pp.1483-1495
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• 2005

TCP/IP is the most commonly used protocol to communicate among servers, and is used in a wide range of applications. Unfortunately, Data transmission through TCP/IP places a very heavy burden on host CPUs. And it hardly makes another job to be processed. So, TOE(TCP/IP Offload Engine) is considered in many servers. But, most of TOE modules tends to not support binary compatibility for standard socket interfaces. So, it has problems that existing applications should be modified and recompiled to get advantage of TOE device. In this paper, to resolve upper problems, we suppose design and implementation of TOE module supporting binary compatibility for standard socket interfaces. Also, it can make a usage of multiple TOEs and NICs simultaneously.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.279-286
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• 2010

RFID reader protocol is an interface between RFID readers and higher (host) such as RFID middlewares and applications. At present, reader protocols provided by vendors are different from each other and there are compatibility problems in environment using heterogeneous readers. In this paper, to solve this problem, an RFID reader which supports LLRP(Low Level Reader Protocol), a well-known standard reader protocol presented by EPCglobal is designed and implemented. It is designed with two modules and supports various interfaces for easy adaptation to various applications. The LLRP protocol is implemented over a embedded LINUX multi-thread environment. It not only supports almost all properties of LLRP, and is designed with flexible hardware/software architecture to meet various requirements.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1405-1408
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• 2005

An embedded system has been applied to many fields including households and industrial sites. In the past, user interface products with simple functions were commercialized .but now user demands are increasing and the system has more various applicable fields due to a high penetration rate of the Internet. Therefore, the demand for embedded system is tend to rise In this paper, we Implementation of an embedded system for image tracking. This system is used a fixed IP for the reliable server operation on TCP/IP networks. A real time broadcasting of video image on the internet was developed by using an USB camera on the embedded Linux system. The digital camera is connected at the USB host port of the embedded board. all input images from the video camera is continuously stored as a compressed JPEG file in a directory at the Linux web-server. And each frame image data from web camera is compared for measurement of displacement Vector. That used Block matching algorithm and edge detection algorithm for past speed. And the displacement vector is used at pan/tilt motor control through RS232 serial cable. The embedded board utilized the S3C2410 MPU Which used the ARM 920T core form Samsung. The operating system was ported to embedded Linux kernel and mounted of root file system. And the stored images are sent to the client PC through the web browser. It used the network function of Linux and it developed a program with protocol of the TCP/IP.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Journal of Periodontal and Implant Science
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• v.44 no.1
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• pp.33-38
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• 2014

Purpose: Autogenous bones are frequently used because of their lack of antigenicity, but good osteoconductive and osteoinductive properties. This study evaluated the biological behavior of perforated and nonperforated cortical block bone grafts. Methods: Ten nonsmoking patients who required treatment due to severe resorption of the alveolar process and subsequent implant installation were included in the study. The inclusion criteria was loss of one or more teeth; the presence of atrophy of the alveolar process with the indication of reconstruction procedures to allow rehabilitation with dental implants; and the absence of systemic disease, local infection, or inflammation. The patients were randomly divided into two groups based on whether they received a perforated (inner surface) or nonperforated graft. After a 6-month healing period, a biopsy was performed and osseointegrated implants were installed in the same procedure. Results: Fibrous connective tissue was evident at the interface in patients who received nonperforated grafts. However, full union between the graft and host bed was visible in those who had received a perforated graft. Conclusions: We found that cortical inner side perforations at donor sites increased the surface area and opened the medullary cavity. Our results indicate an increased rate of graft incorporation in patients who received such perforated grafts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.