• Journal of the Institute of Convergence Signal Processing
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• v.17 no.1
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• pp.1-9
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• 2016

In this paper, for the improvement of quality of service(QoS) performance of heterogeneous networks, multi-cell scheduling is proposed. In order to implement the proposed algorithm, for the recognition of the impact on the throughput performance of users, macro-pico-cells that form distributed architecture were proposed. In operating heterogeneous networks, considering the centralized structure, a macro-RRH(Remote Radio Head) deployment scenario was proposed. For interference mitigation of the proposed system, by applying the optional sub-frame, through CQI(Channel Quality Indicator) measurement for each sub-frame period, constraint conditions were measured according to system situations. For the simplification, the pattern of the same ABS muting was assumed. In the above two multi-cell environments, the algorithm of high-speed load balancing maintenance was proposed.

• The Journal of the Acoustical Society of Korea
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• v.26 no.2
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• pp.87-94
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• 2007

In active sonar system, aspect angle and length of a target can be estimated by calculating the cross-correlation between left and right split-beams of a LFM(Linear Frequency Modulated) signal. However, high-resolution performances in bearing and range are required to estimate the information of a remote target. Because a certain higher sampling frequency than the Nyquist sampling frequency is required in this performance, an over-sampling process through interpolation method should be required. However, real-time implementation of split-beam processing with over-sampled split-beam outputs on a COTS(commercial off-the-shelf) DSP platform limits its performance because of given throughput and memory capacity. This paper proposes a cumulative processing algorithm for split-beam processing to solve the problems. The performance of the proposed method was verified through some simulation tests. Also, the proposed method was implemented as a real-time system using an ADSP-TS101.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.480-483
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• 2018

In this paper, we study the interference canceling and image sensing processing technology of multiple light sources for high speed transmission in CMOS sensor based visible light communication system. To improve transmission capacity in optical camera communications via image sensors, different data must be transmitted simultaneously from each LED. However, multiple LED light source environments for high-speed transmission can cause interference between adjacent LEDs. In this case, since the visible light communication system generally uses intensity modulation, when a plurality of LEDs transmit data at the same time, it is difficult to accurately detect the respective LEDs due to the light scattering interference of the adjacent LEDs. In order to solve this problem, the ON / OFF state of many LEDs of the light source is accurately recognized by using a dual CMOS sensor, and the spectral estimation technique and the pixel image signal processing technique of each LED are proposed. This technique can accurately recognize multiple LED pixels and improve the total average bit error rate and throughput of a MISO-VLC system.

• The KIPS Transactions:PartB
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• v.13B no.6 s.109
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• pp.579-584
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• 2006

This paper proposes a nonlinear template matching measure, called counting measure, as a signal detection measure that is defined as the number of on pixels in the spot area. It is applied to classify probes for an on-off type DNA chip, where each probe spot is classified as hybridized or not. The counting measure also incorporates the maximum response search method, where the expected signal is obtained by taking the maximum among the measured responses of the various positions and sizes of the spot template. The counting measure was compared to existing signal detection measures such as the normalized correlation and the median for 2390 patient samples tested on the human papiliomavirus (HPV) DNA chip. The counting measure performed the best regardless of whether or not the maximum response search method was used. The experimental results showed that the counting measure combined with the positional search was the most preferable.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.70-75
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• 2005

The efficient hardware design of the the algorithm is important in wide variety of DSP. One example is OFDM(Orthogonal Frequency Division Multiplexing) based WLAN(Wireless Local Area Network) systems which place high requirements on throughput and power consumption on FFT. The output RAM is composed of two banks of $64{\times}W.$ The banks are swapped immediately following the falling edge or the start signal strobe. This bank swapping allows 64-Point FFT to continue Processing samples and to continue filling the alternative bank, without affecting the data flow outputs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.42-47
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• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.179-185
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• 2019

This paper proposes a block-type classification based image binarization for the implementation of the low-power feature extraction algorithm. The proposed method can be implemented with threshold value re-use technique approach when the image divided into $64{\times}64$ macro blocks size and calculating the threshold value for each block type only once. The algorithm is validated based on quantitative results that only a threshold value change rate of up to 9% occurs within the same image/block type. Existing algorithms should compute the threshold value for 64 blocks when the macro block is divided by $64{\times}64$ on the basis of $512{\times}512$ images, but all suggestions can be made only once for best cases where the same block type is printed, and for the remaining 63 blocks, the adaptive threshold calculation can be reduced by only performing a block type classification process. The threshold calculation operation is performed five times when all block types occur, and only the block type separation process can be performed for the remaining 59 blocks, so 93% adaptive threshold calculation operation can be reduced.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.