• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.18 no.7
• /
• pp.56-62
• /
• 2019

The high-precision laser scriber carries out scribing alumina ceramic substrates for manufacturing ultra-small chip resistors. The ceramic substrates are loaded, aligned, scribed, transferred, and unloaded. The entire process is fully automated, thereby minimizing the scribing cycle time of the ceramic substrates and improving the throughput. The scriber consists of the laser optical system, pick-up module of ceramic substrates, pre-alignment module, TH axis drive work table, automation module for substrate loading / unloading, and high-speed scribing control S/W. The loader / unloader unit, which has the greatest influence on the scribing cycle time of the substrates, carries the substrates to the work table that carries out the cutting line work by driving the X and Y axes as well as by adsorbing the ceramic substrates. The loader / unloader unit consists of the magazine up / down part, X-axis drive part for conveying the substrates to the left and right direction, and the vision part for detecting the edge of the substrate for the primary pre-alignment of the substrates. In this paper, the laser scribing machining simulation is performed by applying the instrument mechanism of each component module. Through this study, the scribing machining process is first verified by analyzing the process operation and work area of each module in advance. In addition, the scribing machining process is optimized by comparing and analyzing the scribing cycle time of one ceramic substrate according to the alignment stage module speed.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.13 no.2
• /
• pp.582-596
• /
• 2019

Considering that the existing Long Term Evolution is not suitable for the fast and frequent handovers of high-speed trains, this paper proposes a relay-assisted handover mechanism to solve the problems of long handover authentication time and vulnerable to security attacks. It can achieve mutual authentication for train-ground wireless communication, and data transmission is consistent with one-time pad at the same time. The security analysis, efficiency analysis and simulation results show that the proposed mechanism not only realizes the forward security and resists many common attacks, but also effectively reduces the computational overhead of train antenna during the secure handover process. When the running speed of a train is lower than 500km/h, the handover delay is generally lower than 50ms and the handover outage probability is less than 1.8%. When the running speed of a train is 350km/h, the throughput is higher than 16.4mbps in the process of handover. Therefore, the secure handover mechanism can improve the handover performance of high-speed trains.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.9
• /
• pp.1652-1659
• /
• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.53 no.8
• /
• pp.578-584
• /
• 2004

The CSVM(Current Support Vector Machine) that is a digital architecture performing all phases of recognition process including kernel computing, learning, and recall of SVM(Support Vector Machine) on a chip is proposed. Concurrent operation by parallel architecture of elements generates high speed and throughput. The classification problems of bio data having high dimension are solved fast and easily using the CSVM. Quadratic programming in original SVM learning algorithm is not suitable for hardware implementation, due to its complexity and large memory consumption. Hardware-friendly SVM learning algorithms, kernel adatron and kernel perceptron, are embedded on a chip. Experiments on fixed-point algorithm having quantization error are performed and their results are compared with floating-point algorithm. CSVM implemented on FPGA chip generates fast and accurate results on high dimensional cancer data.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.4 no.2
• /
• pp.369-378
• /
• 2014

The Reed-Muller code is one of the efficient algorithms for multiple bit error correction, however, its high-computation requirement inherent in the decoding process prohibits its use in practical applications. To solve this problem, this paper proposes a graphics processing unit (GPU)-based parallel error control approach using Reed-Muller R(r, m) coding for real-time wireless communication systems. GPU offers a high-throughput parallel computing platform that can achieve the desired high-performance decoding by exploiting massive parallelism inherent in the algorithm. In addition, we compare the performance of the GPU-based approach with the equivalent sequential approach that runs on the traditional CPU. The experimental results indicate that the proposed GPU-based approach exceedingly outperforms the sequential approach in terms of execution time, yielding over 70× speedup.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.18 no.3
• /
• pp.307-314
• /
• 2009

Large area micro pattern replication has promising application potential in many areas. Rolling imprint process has been demonstrated as one of the most competitive processes for such micro pattern replication, because it has advantages in low cost, high throughput and high efficiency. In this paper, we developed a prototype of roll-to-flat(R2F) thermal imprint system for large area micro pattern replication process, which is one of the key processes in the fabrication of flexible displays. Experimental tests were conducted to evaluate the feasibility of system and the parameters' effect on the process, such as flat mold temperature, loading pressure and rolling speed. 100mm $\times$ 100mm stainless steel flat mold and commercially available polycarbonate sheets were used for the tests. The experimental results showed that the developed R2F system is suitable for fabrication of various micro devices with micro pattern over large area.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
• /
• v.21 no.1
• /
• pp.9-22
• /
• 2023

Spin-off pyroprocessing technology and inert anode materials to replace the conventional carbon-based smelting process for critical materials were introduced. Efforts to select inert anode materials through numerical analysis and selected experimental results were devised for the high-throughput reduction of oxide feedstocks. The electrochemical properties of the inert anode material were evaluated, and stable electrolysis behavior and CaCu generation were observed during molten salt recycling. Thereafter, CuTi was prepared by reacting rutile (TiO₂) with CaCu in a Ti crucible. The formation of CuTi was confirmed when the concentration of CaO in the molten salt was controlled at 7.5mol%. A laboratory-scale electrorefining study was conducted using CuTi(Zr, Hf) alloys as the anodes, with a Ti electrodeposit conforming to the ASTM B299 standard recovered using a pilot-scale electrorefining device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.185-188
• /
• 2001

Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2 \; (PN_2)$ gas, slurry filter and high spray bar were installed. Our experimental results show that DIW pressure and $PN_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter. Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.51 no.5
• /
• pp.191-195
• /
• 2002

Chemical mechanical Polishing (CMP) process is widely used for the global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2$ ($PN_2$) gas, point of use (POU) slurry filler and high spray bar (HSB) were installed. Our experimental results show that DW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.5
• /
• pp.361-368
• /
• 2003

A new high-speed direct digital frequency synthesizer using a low power pipelined parallel accumulator is proposed. The proposed pipelined parallel accumulator uses both pipelining and paralleling techniques to increase speed and to reduce power consumption. The 2-pipelined 2-parallel accumulator only consumes 66% and 69% power of the 4-pipelined accumulator and the 4-parallel accumulator respectively with the same throughput. The proposed accumulator can achieve higher throughput with smaller area and less power consumption in lower clock frequency. All circuit simulations and implementations are based on a 0.35um CMOS process with VCC = 3.3V.