• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2783-2790
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.31 no.4
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• pp.221-228
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• 2019

Experimental investigation was performed to analyze the flow field characteristics and power generation performance for a shroud tidal power generation system. Electrical power output was compared with the rotational speed of the turbine blade and electric load connected to the generator for various flow velocity. As the electrical load decreased, the speed of the turbine increased rapidly and reached by about 2 times. The power output also increased remarkably with the decrease of load, and then decreased after maximum power point. In addition, the maximum power point appeared at high electrical loads as the experimental flow velocity increased. These results of the flow field characteristics and power generation performance analysis of the shroud tidal power generation system variation with the flow velocity conditions and electrical load are expected to be the basic data necessary for the development of efficient shroud tidal power generation system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2002.05a
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• pp.23-28
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• 2002

This paper describes the machining characteristics of the $MoSi_2$ based composites by electric discharge drilling with various tubular electrodes, besides, Hardness characteristics and microstructures of $Nb/MoSi_2$ laminate composites were evaluated from the variation of fabricating conditions such as preparation temperature, applied pressure and pressure holding time. $MoSi_2$ -based composites has been developed in new materials for jet engine of supersonic-speed airplanes and gas turbine for high- temperature generator. Achieving this objective may require new hard materials with high strength and high temperature-resistance. However, With the exception of grinding, traditional machining methods are not applicable to these new materials. Electric discharge machining (EDM) is a thermal process that utilizes a spark discharge to melt a conductive material, the tool electrode being almost non-unloaded, because there is no direct contact between the tool electrode and the workpiece. By combining a nonconducting ceramics with more conducting ceramic it was possible to raise the electrical conductivity. From experimental results, it was found that the lamination from Nb sheet and $MoSi_2$ powder was an excellent strategy to improve hardness characteristics of monolithic $MoSi_2$. However, interfacial reaction products like (Nb, Mo)$SiO_2$ and $Nb_2Si_3$ formed at the interface of $Nb/MoSi_2$ and increased with fabricating temperature. $MoSi_2$ composites which a hole drilling was not possible by the conventional machining process, enhanced the capacity of ED-drilling by adding $NbSi_2$ relative to that of SiC or $ZrO_2$ reinforcements.

• The Journal of the Acoustical Society of Korea
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• v.39 no.3
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• pp.151-162
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• 2020

This paper presents an acoustic inversion method for estimating the bubble size distribution. The estimation error of the attenuation coefficient represented by a Fredholm integral equation of the first kind is defined as an objective function, and an optimal solution is found by applying the Levenberg-Marquardt (LM) method. In order to validate the effectiveness of the inversion method, numerical simulations using two types of bubble distribution are performed. In addition, a series of experiments are carried out in a water tank (1.0 m × 0.54 m × 0.6 m), using bubbles generated by three different generators. Images of the distributed bubbles are obtained by a high-speed camera, and the insertion losses of the bubble layer are measured using a source and a hydrophone. The image is post-processed to glance a distribution characteristics of each bubble generator. Finally, the size distribution of bubbles is estimated by applying the inversion method to the measured insertion loss. From the inversion results, it was observed that the number of bubbles increases exponentially as the bubble size decreases, and then increases again after the local peak at 70 ㎛ - 120 ㎛.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.1
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• pp.8-15
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• 2018

New methodology for probabilistic reliability based grid expansion planning of HVDC in power system including Wind Turbine Generators(WTG) is developed in this paper. This problem is focused on scenario based optimal selection technique to decide best connection bus of new transmission lines of HVDC in view point of adequacy reliability in power system including WTG. This requires two kinds of modeling and simulation for reliability evaluation. One is how is reliability evaluation model and simulation of WTG. Another is to develop a failure model of HVDC. First, reliability evaluation of power system including WTG needs multi-state simulation methodology because of intermittent characteristics of wind speed and nonlinear generation curve of WTG. Reliability methodology of power system including WTG has already been developed with considering multi-state simulation over the years in the world. The multi-state model already developed by authors is used for WTG reliability simulation in this study. Second, the power system including HVDC includes AC/DC converter and DC/AC inverter substation. The substation is composed of a lot of thyristor devices, in which devices have possibility of failure occurrence in potential. Failure model of AC/DC converter and DC/AC inverter substation in order to simulate HVDC reliability is newly proposed in this paper. Furthermore, this problem should be formulated in hierarchical level II(HLII) reliability evaluation because of best bus choice problem for connecting new HVDC and transmission lines consideration. HLII reliability simulation technique is not simple but difficult and complex. CmRel program, which is adequacy reliability evaluation program developed by authors, is extended and developed for this study. Using proposed method, new HVDC connected bus point is able to be decided at best reliability level successfully. Methodology proposed in this paper is applied to small sized model power system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.2
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• pp.319-326
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• 2020

PRNGs(Pseudorandom number generators) are essential for generating encryption keys for to secure online communication. A bitstream generated by the PRNG must be generated at high speed to encrypt the big data effectively in a symmetric key cryptosystem and should ensure the randomness of the level to pass through the several statistical tests. CA(Cellular Automata) based PRNGs are known to be easy to implement in hardware and to have better randomness than LFSR based PRNGs. In this paper, we design PRNGs based on PMLCA(Programable Maximum Length CA) that can generate effective key sequences in symmetric key cryptosystem. The proposed PRNGs generate bit streams through nonlinear control method. First, we design a PRNG based on an (m,n)-cell PMLCA ℙ with a single complement vector that produces linear sequences with the long period and analyze the period and the generating polynomial of ℙ. Next, we design an (m,n)-cell PC-MLCA based PRNG with two complement vectors that have the same period as ℙ and generate nonlinear sequences, and analyze the location of outputting the nonlinear sequence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.