• 대한전자공학회논문지SD
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• 제46권7호
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• pp.1-6
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• 2009

본 논문은 DRAM에서 DBI (Data Bus Inversion)를 이용한 새로운 방식의 High Speed 아키텍쳐를 설명하고자한다. DBI는 SSO와 LSI와 같은 잘 알려진 문제를 감소시키기 위한 방식중의 하나이다. 본 논문에서는 Analog Majority Voter(AMV), DBI Flag에 의한 GIO 제어회로, 새로운 SSO Algorithm과 같은 많은 아키텍쳐들이 Data Bus의 천이(Toggle) 개수를 줄이기 위해서 제안되었다. DBI Flag에 의해 GIO데이터 반전 여부를 결정되기 때문에 파워 소모가 감소될 수 있고, 데이터 Eye diagram도 40ps이상 증가될 수 있게 되었다. 제안된 DBI Scheme을 이용하였을 때 High speed 동작에서 거의 안정한 SI특성을 얻을 수 있게 됐다. 90nm CMOS Technology를 이용하여 제조되었다.

• Journal of information and communication convergence engineering
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• 제1권4호
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• pp.177-182
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• 2003

Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for rate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing codes with high speed in a time. However, the speed of the current circuits may set limits to the codes used. With increasing speeds of the circuits in the future, the proposed technique may become a tempting choice for decoding convolutional coding with long constraint lengths.

• Journal of Power Electronics
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• 제18권4호
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 전자공학회논문지A
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• 제32A권3호
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• pp.25-37
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• 1995

The phenomenological loss equivalence method incorporated into the wideband lossy transmission line model is applied to the characterization of high desity digital transmission lines. The pulse propagation characteristics are analyzed using the calculated frequency characteristics and the discrete Fourier transformation. This approach has been verified by comparing the calculated frequency characteristics with the FEM and the esperimental results. This method is very suitable for computer-aided analysis of high density/high speed interconnection circuits because of the simple calculation as well as the calculation accuracy. We have found that pulse ftransmission speed and dispersion of hgih density digital transmission lines can be optimized by managing the conductor and dielectric losses in addition to the impedance matching.

• 한국통신학회논문지
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• 제12권4호
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• pp.347-356
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• 1987

本 論文에서는 高速 光 디지털 傳送시스템과 같은 高速 unipolar 信號 傳送시스템에 適合한 새로운 mBIZ 傳送路符號를 提案하였다. mBIZ符號는 情報信號系列 傳送速度를 $\frac{(m+1)}{m}$ 만큼 速度變換한 後 m 비트마다 補助 서어비스 비트 하나를 揷入한 信號系列과 出力傳送路符號系列의 한 비트를 遲延시킨 信號系列을 Exclusive NOR하여 符號化하기 때문에 redundancy를 줄일 수 있을 뿐만 아니라 復號回路 역시 간단하게 構成할 수 있다. mBIZ符號는 回符號連積數를 (m+1)비트 이내로 抑壓할 수 있으며 傳送路符號系列의 마크率이 1/2이기 때문에 電力 스펙트럼에 存在하는 高低周波 成分들을 抑壓할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.353-356
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• 1996

Ultra-high-speed analog and digital ICs (integrated circuits) fur 10Gbit/sec optical communication systems have been designed, fabricated and analyzed in this research. These circuits, which are laser diode (LD) driver, pre-amplifier, automatic gain controlled (AGC) amplifier, limiting amplifier and decision circuit, have been implemented with AIGaAs/GaAs heterojunction bipolar transistors (HBTs). The optimized AIGaAs/GaAs HBTs for the 10Gbps circuits in this work showed the cutoff and maximum oscillation frequencies of 65㎓ and 53㎓, respectively. It is demonstrated in this paper that the 10Gbps optical communication system can be realized with the ICs designed and fabricated using AlGaAs/GaAs HBTs.

• Journal of Power Electronics
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• 제6권2호
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• 한국철도학회논문집
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• 제20권5호
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• pp.602-611
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• 2017

철도시스템에서 이동 중인 열차와 지상과의 정보교환은 위치검지, 열차제어 등 다양한 분야에서 매우 중요한 역할을 수행하고 있다. 열차와 지상간의 정보전송을 위한 매체로 대부분 궤도회로가 사용되어 왔으나, 궤도회로는 지상에 선로를 따라 연속적으로 설치되어야 하므로 설치 및 유지보수 비용의 증대를 초래한다. 이러한 문제를 해결하고자 최근에는 연속적인 정보전송(무선통신)과 불연속적인 정보전송(트랜스폰더)을 혼합하는 방식으로 변화되고 있다. 본 연구에서는 400km/h의 고속으로 이동하는 열차에서 지상과 차상간 정보전송이 가능한 트랜스폰더 시스템을 개발하기 위하여, 현장설치 및 유지보수가 효율적인 수동형 태그에 구동전원을 공급하기 위한 무선전력전송용 리더 및 태그 안테나를 설계하고, 시뮬레이션 및 시작품 제작을 통하여 그 성능을 확인하였다.