• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.167-173
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• 2005

The isolation of the series PIN diode switch is restricted by the parallel capacitance of PIN diode and the switch driver circuit limits switching speed of PIN diode switch. To overcome these problems, a high isolation and high switching speed Pin diode switch is proposed adapting the parallel resonant inductance and TTL compatible switch driver circuit. The measurement results of the 3 GHz PM diode switch show 1 GHz frequency band, less than 1.5 dB insertion loss, 65 dB isolation, more than 15 dB return loss and less than 30 ns switching speed. In particular the 3 GHz PIN diode switch using the parallel resonant inductance exhibits the improvement of isolation by 15 dB.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1020-1022
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• 1993

The speed control associated with do send motors for direct-drive applications of mobile robot is considered. In odor to the high-performance operation of dc servo motor, drive circuits is controlled Pulse Width Modulations. In this case, PWM driving circuit has nonliner charactristics. This circuit composed of H-type bridge with freewheeling diodes in odor to deal with storage energy of motor's inductance and also control method is developed. At resultes, speed charactristics of motor is shown lineristics. In oder to speed control of motor. The opertion of phase-locked servo system is described and a linear discrete model is developed to their behavior. Thise model discussed are the design problems, speed variation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.457-460
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• 1998

Present paper is devoted to the brief analysis of the present state and the prospects for the future of technology of the high frequency devices and high speed integrated circuits based on the $A_{3}B_{5}$ semiconductor compounds, including the $A_{3}B_{5}$-heterostructures, in the republics of the former USSR. tunneling quantum well-structures were widely used.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.704-706
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• 1993

This paper, introduces a Current-fed type High-Frequency Inverter with self turning devices. By replacing Thyrisors used for power source of heat treatment with high speed switching element, MOSFET in current type Inverter, the proposed Inverter makes high speed performance with several 100kHz. This paper also depicts some operating principles of the proposed circuits and general operating characteristics. Steady state solution on state variables in analysis of the proposed circuit is described generally by using normalized parameter and its characteristics depending on separate ratio(n) is also shown.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.1-7
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• 1998

This paper reports a dispersion compensation technique to implement tje distortionless transmission line by satisfying the heaviside conditon. Because of the skin depth for aconductor, compensation condition is dependent on the freuqncy variation. For this reason, first, the resistance have been chaacterized in awide range of frequencies, and then found the effective conductivity of the substrate which satisfied the heaviside condition. The phase velocity and the characteristics impedance are prresented nearly constant over a wideband frequency range.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.735-738
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• 2002

This paper a new simple PWM (Pulse Width Modulation) signal generation based on modified relaxation oscillator is introduced. Its advantages of the proposed principle are that the precise PWM signal can be easily achieved with a high frequency range up to several megahertz and a low-voltage power supply. The proposed circuit can accept either voltage or current modulating signal. It is very suitable for developing into Integrated Circuits (ICs) form in communication applications. The simulation and experimental results are also depicted, they shown good agreement with theoretical anticipation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.