• 한국통신학회논문지
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• 제21권6호
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• pp.1425-1429
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• 1996

누락펄스가 발생할 시 PRI 분석을 위한 전형적인 sequence search 알고리즘은 harmonic 문제를 발생시킨다. 본 논문에서 이러한 harmonic 문제를 해결할 수 있는 PRI 분석 알고리즘을 제안한다. 분석해야 할 전체 PRI 범위를 harmonic이 없도록 subband 로 나눈 후, sequence search를 forward 및 backward로 행한다. 전형적인 sequence search 알고리즘에 비하여 제안한 알고리즘의 성능이 증대된다.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2018년도 춘계 학술논문 발표대회
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• pp.185-186
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• 2018

The slabfrom, which is commonly used in construction sites, has drawbacks in that the workability of the workers is reduced due to their heavy weight. This study investigates the possibility of design optimization of euro form between structural stability and weight using harmonic search algorithm. The harmonic search algorithm is a metaheuristic optimization technique that obtains multiple optimal solution candidates through iterative. As a result of multiple attempts of optimization through the algorithm, it was possible to design the formwork which is structurally stable and light in weight than the existing formwork.

• Journal of Information Processing Systems
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• 제14권5호
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• pp.1237-1253
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• 2018

Harmony search algorithm is an emerging meta-heuristic optimization algorithm, which is inspired by the music improvisation process and can solve different optimization problems. In order to further improve the performance of the algorithm, this paper proposes an improved harmony search algorithm. Key parameters including harmonic memory consideration (HMCR), pitch adjustment rate (PAR), and bandwidth (BW) are optimized as the number of iterations increases. Meanwhile, referring to the genetic algorithm, an improved method to generate a new crossover solutions rather than the traditional mechanism of improvisation. Four complex function optimization and pressure vessel optimization problems were simulated using the optimization algorithm of standard harmony search algorithm, improved harmony search algorithm and exploratory harmony search algorithm. The simulation results show that the algorithm improves the ability to find global search and evolutionary speed. Optimization effect simulation results are satisfactory.

• Journal of Power Electronics
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• 제19권6호
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• pp.1458-1466
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• 2019

Multilevel inverters have appeared as a successful and utilitarian solution in many power applications. The prime objective of an inverter is to keep the fundamental component of the output voltage of a multilevel inverter at a preferred value. Equally important is the need to keep the harmonic components in the output voltage within stated harmonic limits. Therefore, the basis of this research is to develop a harmonic minimization function that optimizes the switching angles of cascaded H-bridge multilevel inverter. Due to benefits of the Cuckoo Search (CS) algorithm, it is applied to determine the switching angles, which are further used to generate the switching pattern for firing the H-bridges of multilevel inverter. Simulation results are compared with SPWM based firing scheme. The switching frequency for SPWM firing scheme is taken as 200 Hz since the switching losses are increased when switching frequency is high. To validate the ability of Cuckoo Search optimized firing scheme in minimization of harmonics, experimental results obtained from hardware prototype of Five Level Cascaded H-Bridge Multilevel Inverter equipped with a FPGA controller are presented to verify the simulation results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권4호
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• pp.1961-1974
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• 2019

In this letter, a harmonic-mean-based dual-antenna selection scheme at relay node is proposed in two-way relaying networks (TWRNs). With well-designed distributed orthogonal concatenated Alamouti space-time block code (STBC), a dual-antenna selection problem based on the instantaneous achievable sum-rate criterion is formulated. We propose a low-complexity selection algorithm based on the harmonic-mean criterion with linearly complexity $O(N_R)$ rather than the directly exhaustive search with complexity $O(N^2_R)$. From the analysis of network outage performance, we show that the asymptotic diversity gain function of the proposed scheme achieves as $1/{\rho}{^{N_R-1}}$, which demonstrates one degree loss of diversity order compared with the full diversity. This slight performance gap is mainly caused by sacrificing some dual-antenna selection freedom to reduce the algorithm complexity. In addition, our proposed scheme can obtain an extra coding gain because of the combination of the well-designed orthogonal concatenated Alamouti STBC and the corresponding dual-antenna selection algorithm. Compared with the common-used selection algorithms in the state of the art, the proposed scheme can achieve the best performance, which is validated by numerical simulations.

• 전기전자학회논문지
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• 제21권4호
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• pp.416-419
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• 2017

본 논문에서는 고속 DDR3/DDR4 SDRAM을 위한 새로운 디지털 지연고정루프 (delay-locked loop: DLL)를 제안한다. 제안하는 디지털 DLL은 디지털 지연라인의 boundary switching 문제에 의한 jitter 증가 문제를 제거하기 위하여 위상보간 (phase interpolation) 방식의 파인지연라인 (fine delay line)을 채택하였다. 또한, 제안하는 디지털 DLL은 harmonic lock 문제를 제거하기 위하여 새로운 점진직 검색 (gradual search) 알고리즘을 사용한다. 제안하는 디지털 DLL은 1.1V, 38-nm CMOS DRAM 공정으로 설계되었으며, 0.25-2.0 GHz의 주파수 동작 영역을 가진다. 2.0 GHz에서 1.1 ps의 피크-투-피크 (p-p) 지터를 가지며, 약 13 mW의 전력소모를 가진다.

• 한국통신학회논문지
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• 제29권7C호
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• pp.962-970
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• 2004

본 논문에서는 TI사의 부동소수점 DSP인 TMS320C6701$^{TM}$을 이용한 2.4kbps EHSX(Enhanced Harmonic Stochastic Excitation) 음성부호화기의 실시간 구현 방법에 대해서 논한다. EHSX는 4khz의 대역폭을 갖는 음성신호를 2.4kbps의 비트율을 갖는 압축 패킷으로 변환하는 부호화 방법으로, 유/무성음에 따라 하모닉(Harmonic) 여기 부호화 방법과 CELP 부호화 방법을 선택적으로 사용하는 구조를 갖는다. 본 논문에서는 이러한 EHSX의 실시간 구현을 위해 연산량의 큰 비중을 차지하는 CELP 분석의 코드북 검색부분과 일부 IIR 필터링 부분에 대한 고정소수점 변환 방법과, 부호화시 하모닉 검색 및 피치 검색방법에 대한 알고리즘 상 연산량 감소 방법, DSP의 구조를 고려한 코드를 배치방법 등 연산량을 감소시키기 위한 최적화 방법을 제시한다. 설계된 음성 부호화기는 PESQ(perceptual evaluation of speech quality) ITU-T Recommendation P.862를 이용한 음질 평가 결과로서 약MOS 3.28을 얻었으며, 실시간으로 압축 및 복원을 수행한다.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• 한국초전도ㆍ저온공학회논문지
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• 제23권4호
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• pp.39-43
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• 2021

This study deals with the ferromagnetic shims design based on the spherical harmonic coefficient reduction method. The design method using the sequential search method is an intuitive method and has the advantage of quickly reaching the optimal result. The study was conducted for a 400 MHz all-REBCO magnet, which had difficulty in shimming due to the problem of SCF (screening current induced field). The initial field homogeneity of the magnet was measured to be 233.76 ppm at 20 mm DSV (Diameter Spherical Volume). In order to improve the field homogeneity of the magnet, the ferromagnetic shim with a thickness of 1 mil to 11 mil was constructed by a design method in which sequential search algorithm was applied. As a result, the field homogeneity of the magnet could be significantly improved to 0.24 ppm at 20 mm DSV and 0.05 ppm at 10 mm DSV.

• 전기전자학회논문지
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• 제22권4호
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• pp.1158-1162
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• 2018

안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수 증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ~ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는 MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.