• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1425-1429
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• 1996

A conventional sequence search algorithm for PRI analysis occurs the harmonic problem under missing pulses. An improved PRI analysis algorithm is proposedto remedy the harmonic problem. After dividing an overall PRI range into subbands withoug harmonic, a sequence search is done into forward and backward in time. The proposed algorithm increases the preformance compared with that of conventional sequence search algorithm.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2018.05a
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• pp.185-186
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• 2018

The slabfrom, which is commonly used in construction sites, has drawbacks in that the workability of the workers is reduced due to their heavy weight. This study investigates the possibility of design optimization of euro form between structural stability and weight using harmonic search algorithm. The harmonic search algorithm is a metaheuristic optimization technique that obtains multiple optimal solution candidates through iterative. As a result of multiple attempts of optimization through the algorithm, it was possible to design the formwork which is structurally stable and light in weight than the existing formwork.

• Journal of Information Processing Systems
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• v.14 no.5
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• pp.1237-1253
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• 2018

Harmony search algorithm is an emerging meta-heuristic optimization algorithm, which is inspired by the music improvisation process and can solve different optimization problems. In order to further improve the performance of the algorithm, this paper proposes an improved harmony search algorithm. Key parameters including harmonic memory consideration (HMCR), pitch adjustment rate (PAR), and bandwidth (BW) are optimized as the number of iterations increases. Meanwhile, referring to the genetic algorithm, an improved method to generate a new crossover solutions rather than the traditional mechanism of improvisation. Four complex function optimization and pressure vessel optimization problems were simulated using the optimization algorithm of standard harmony search algorithm, improved harmony search algorithm and exploratory harmony search algorithm. The simulation results show that the algorithm improves the ability to find global search and evolutionary speed. Optimization effect simulation results are satisfactory.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1458-1466
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• 2019

Multilevel inverters have appeared as a successful and utilitarian solution in many power applications. The prime objective of an inverter is to keep the fundamental component of the output voltage of a multilevel inverter at a preferred value. Equally important is the need to keep the harmonic components in the output voltage within stated harmonic limits. Therefore, the basis of this research is to develop a harmonic minimization function that optimizes the switching angles of cascaded H-bridge multilevel inverter. Due to benefits of the Cuckoo Search (CS) algorithm, it is applied to determine the switching angles, which are further used to generate the switching pattern for firing the H-bridges of multilevel inverter. Simulation results are compared with SPWM based firing scheme. The switching frequency for SPWM firing scheme is taken as 200 Hz since the switching losses are increased when switching frequency is high. To validate the ability of Cuckoo Search optimized firing scheme in minimization of harmonics, experimental results obtained from hardware prototype of Five Level Cascaded H-Bridge Multilevel Inverter equipped with a FPGA controller are presented to verify the simulation results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1961-1974
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• 2019

In this letter, a harmonic-mean-based dual-antenna selection scheme at relay node is proposed in two-way relaying networks (TWRNs). With well-designed distributed orthogonal concatenated Alamouti space-time block code (STBC), a dual-antenna selection problem based on the instantaneous achievable sum-rate criterion is formulated. We propose a low-complexity selection algorithm based on the harmonic-mean criterion with linearly complexity $O(N_R)$ rather than the directly exhaustive search with complexity $O(N^2_R)$. From the analysis of network outage performance, we show that the asymptotic diversity gain function of the proposed scheme achieves as $1/{\rho}{^{N_R-1}}$, which demonstrates one degree loss of diversity order compared with the full diversity. This slight performance gap is mainly caused by sacrificing some dual-antenna selection freedom to reduce the algorithm complexity. In addition, our proposed scheme can obtain an extra coding gain because of the combination of the well-designed orthogonal concatenated Alamouti STBC and the corresponding dual-antenna selection algorithm. Compared with the common-used selection algorithms in the state of the art, the proposed scheme can achieve the best performance, which is validated by numerical simulations.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.962-970
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• 2004

This paper presents an efficient implementation of the 2.4 kbps EHSX(Enhanced Harmonic Stochastic Excitation) speech coder on a TMS320C6701$^{TM}$ floating-point digital signal processor. The EHSX speech codec is based on a harmonic and CELP(Code Excited Linear Prediction) modeling of the excitation signal respectively according to the frame characteristic such as a voiced speech and an unvoiced speech. In this paper, we represent the optimization methods to reduce the complexity for real-time implementation. The complexity in the filtering of a CELP algorithm that is the main part for the EHSX algorithm complexity can be reduced by converting program using floating-point variable to program using fixed-point variable. We also present the efficient optimization methods including the code allocation considering a DSP architecture and the low complexity algorithm of harmonic/pitch search in encoder part. Finally, we obtained the subjective quality of MOS 3.28 from speech quality test using the PESQ(perceptual evaluation of speech quality), ITU-T Recommendation P.862 and could get a goal of realtime operation of the EHSX codec.c.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Progress in Superconductivity and Cryogenics
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• v.23 no.4
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• pp.39-43
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• 2021

This study deals with the ferromagnetic shims design based on the spherical harmonic coefficient reduction method. The design method using the sequential search method is an intuitive method and has the advantage of quickly reaching the optimal result. The study was conducted for a 400 MHz all-REBCO magnet, which had difficulty in shimming due to the problem of SCF (screening current induced field). The initial field homogeneity of the magnet was measured to be 233.76 ppm at 20 mm DSV (Diameter Spherical Volume). In order to improve the field homogeneity of the magnet, the ferromagnetic shim with a thickness of 1 mil to 11 mil was constructed by a design method in which sequential search algorithm was applied. As a result, the field homogeneity of the magnet could be significantly improved to 0.24 ppm at 20 mm DSV and 0.05 ppm at 10 mm DSV.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.