• International Journal of Computer Science & Network Security
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• v.23 no.10
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• pp.49-56
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• 2023

Computer architecture serves as a link between application requirements and underlying technology capabilities such as technical, mathematical, medical, and business applications' computational and storage demands are constantly increasing. Machine learning these days grown and used in many fields and it performed better than traditional computing in applications that need to be implemented by using mathematical algorithms. A mathematical algorithm requires more extensive and quicker calculations, higher computer architecture specification, and takes longer execution time. Therefore, there is a need to improve the use of computer hardware such as CPU, memory, etc. optimization has a main role to reduce the execution time and improve the utilization of computer recourses. And for the importance of execution time in implementing machine learning supervised module linear regression, in this paper we focus on optimizing machine learning algorithms, for this purpose we write a (Diabetes prediction program) and applying on it a Practical Swarm Optimization (PSO) to reduce the execution time and improve the utilization of computer resources. Finally, a massive improvement in execution time were observed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.425-437
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• 2017

For efficient hardware (HW) implementation of elliptic curve cryptography (ECC), various sub-modules for the underlying finite field operations should be implemented efficiently. Among these sub-modules, modular inversion (MI) requires the most computation; therefore, its performance might be a dominant factor of the overall performance of an ECC module. To determine the most efficient MI algorithm for an HW ECC module, we implement various classes of MI algorithms and analyze their performance. In contrast to the common belief in previous research, our results show that the right-shift binary inversion (RS) algorithm performs well when implemented in hardware. In addition, we present optimization methods to reduce the area overhead and improve the speed of the RS algorithm. By applying these methods, we propose a new RS-variant that is both fast and compact. The proposed MI module is more than twice as fast as the other two classes of MI: shifting Euclidean (SE) and left-shift binary inversion (LS) algorithms. It consumes only 15% more area and even 5% less area than SE and LS, respectively. Finally, we show that how our new method can be applied to optimize an HW ECC module.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.1
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• pp.113-118
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• 2001

In this paper, we implement modules of the MPEG-2 AAC decoder using VHDL. Tools of Huffman decoder, inverse quantizer and high-density filter bank which are necessary for the AAC decoder. We designed the high speed Huffman decoder using the method of octal tree search algorithm, and reduced computational time of filter bank using IFFT. Also, we use table of computation result for an exponential calculation of Inverse quantizer in fixed-point hardware, and reduced the size of table using linear interpolation. Modules implemented by hardware through optimization work in real time at low clock frequency are possible to reduce the system size.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.4
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• pp.265-276
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• 2004

Genetic Algorithm(GA), that is shown stable performance to find an optimal solution, has been used as a method of solving large-scaled optimization problems with complex constraints in various applications. Since it takes so much time to execute a long computation process for iterative evolution and adaptation. In this paper, a hardware-based adaptive GA was proposed to reduce the serious computation time of the evolutionary process and to improve the accuracy of convergence to optimal solution. The proposed GA, based on steady-state model among continuos generation model, performs an adaptive mutation process with consideration of the evolution flow and the population diversity. The drawback of the GA, premature convergence, was solved by the proposed adaptation. The Performance improvement of convergence accuracy for some kinds of problem and condition reached to 5-100% with equivalent convergence speed to high-speed algorithm. The proposed adaptive GAP(Genetic Algorithm Processor) was implemented on FPGA device Xilinx XCV2000E of EHW board for face recognition.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.1-8
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• 2003

This paper presents a novel application method of H$_{\infty}$ optimization method to the design of Power System Stabilizer(PSS) and experimental results through hardware simulator. The approach is focused on decision of performance index and selection strategy of weighting functions together with its tuning for direct design. As the Purpose of the PSS is to increase system damping at very narrow frequency band, weighting functions are determined differently from the case of general servo system control. The designed PSS was confirmed through experiments on a hardware simulator.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.102-105
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• 1993

The objective of this study is to solve the operation scheduling problem of plural battery energy storage systems (BESS), and to find useful intonation from its result. Unlike conventional energy storage system, BESS has on hardware characteristics such as high efficiency, fast-acting response and operational loss. Considering rate constraints of thermal unit power as well as hardware characteristics of BESS, the operation scheduling has an intricated problem. In order to solve this optimization problem, we use successive approximations dynamic programming. In two types of operation, the proposed algorithm is applied to test system. one is daily optimal operation, the other weekly optimal operation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• Archives of Plastic Surgery
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• v.49 no.5
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• pp.642-647
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• 2022

Hemifacial microsomia (HFM) is a complex congenital condition with heterogeneous malformations of the facial skeleton that almost always involves mandibular hypoplasia. Here we introduce a unique case in which a patient with HFM had initially successful optimization of facial symmetry using a polyetheretherketone implant for mandibular augmentation. However, multiple factors associated with the intraoperative and postoperative course, including hardware failure and infection, led to diminished mechanical strength of the mandible, ultimately resulting in a mandibular fracture. In this unique case presentation of HFM, we discuss the various factors that contributed to mandibular weakness and increased susceptibility to fracture.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.165-168
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• 2000

In this paper, we propose a method, an optimized architecture of a device with an image signal process of a field unit to minimize the flick phenomenon that happens in direction of a color temperature at a color tone change. The proposed IIR loop filter has an optimized architecture and reduced hardware compared with previous filters. In order to achieve the optimization for the hardware complexity. It is designed by time-multiplexing architecture. The proposed IIR loop filter is synthesized by using the STD90 0.35um cell library.