• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.2
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• pp.728-741
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• 2015

Stereo vision has become an important technical issue in the field of 3D imaging, machine vision, robotics, image analysis, and so on. The depth map extraction from stereo video is a key technology of stereoscopic 3D video requiring stereo correspondence algorithms. This is the matching process of the similarity measure for each disparity value, followed by an aggregation and optimization step. Since it requires a lot of computational power, there are significant speed-performance advantages when exploiting parallel processing available on processors. In this situation, multi-core CPU may allow many parallel programming technologies to be realized in users computing devices. This paper proposes parallel implementations for calculating disparity map using a shared memory programming and exploiting the streaming SIMD extension technology. By doing so, we can take advantage both of the hardware and software features of multi-core processor. For the performance evaluation, we implemented a parallel SAD algorithm with OpenMP and SSE2. Their processing speeds are compared with non parallel version on stereoscopic streaming video. The experimental results show that both technologies have a significant effect on the performance and achieve great improvements on processing speed.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1274-1285
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• 2015

This paper deals with model reference adaptive system (MRAS) speed estimators based on a secondary flux for linear induction motors (LIMs). The operation of these estimators significantly depends on an adaptation mechanism. Fixed-gain PI controller is the most common adaptation mechanism that may fail to estimate the speed correctly in different conditions, such as variation in machine parameters and noisy environment. Two adaptation mechanisms are proposed to improve LIM drive system performance, particularly at very low speed. The first adaptation mechanism is based on fuzzy theory, and the second is obtained from an LIM mechanical model. Compared with a conventional PI controller, the proposed adaptation mechanisms have low sensitivity to both variations of machine parameters and noise. The optimum parameters of adaptation mechanisms are tuned using an offline method through chaotic optimization algorithm (COA) because no design criterion is given to provide these values. The efficiency of MRAS speed estimator is validated by both numerical simulation and real-time hardware-in-the-loop (HIL) implementations. Results indicate that the proposed adaptation mechanisms improve performance of MRAS speed estimator.

• Journal of Korean Society of Transportation
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• v.14 no.1
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• pp.51-67
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• 1996

The optimal path-finding problem becomes complicated when multiple variables are simultaneously considered such as physical route length, degree of congestion, traffic capacity of intersections, number of intersections and lanes, and existence of free ways. Therefore, many researchers in various fields (management science, computer science, applied mathematics, production planning, satellite launching) attempted to solve the problem by ignoring many variables for problem simplification, by developing intelligent algorithms, or by developing high-speed hardware. In this research, an integration of expert system technique and case-based reasoning in high level with a conventional algorithms in lower level was attempted to develop an optimal path-finding system. Early application of experienced driver's knowledge and case data accumulated in case base drastically reduces number of possible combinations of optimal paths by generating promising alternatives and by eliminating non-profitable alternatives. Then, employment of a conventional optimization algorithm provides faster search mechanisms than other methods such as bidirectional algorithm and $A^*$ algorithm. The conclusion obtained from repeated laboratory experiments with real traffic data in Seoul metropolitan area shows that the integrated approach to finding optimal paths with consideration of various real world constraints provides reasonable solution in a faster way than others.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1396-1406
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• 2016

A novel controller design is presented for the recently proposed electric springs (ESs). The dynamic modeling is analyzed first, and the initial Bode diagram is derived from the s-domain transfer function in the open loop. The design objective is set according to the characteristics of a minimum phase system. Step-by-step optimizations of the Bode diagram are provided to illustrate the proposed controller, the design of which is different from the classical multistage leading/lagging design. The final controller is the accumulation of the transfer function at each step. With the controller and the recently proposed δ control, the critical load voltage can be regulated to follow the desired waveform precisely while the fluctuations and distortions of the input voltage are passed to the non-critical loads. Frequency responses at any point can be modified in the Bode diagram. The results of the modeling and controller design are validated via simulations. Hardware and software designs are provided. A digital phase locked loop is realized with the platform of a digital signal processor. The effectiveness of the proposed control is also validated by experimental results.

• Journal of Korean Institute of Industrial Engineers
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• v.1 no.1
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• pp.41-56
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• 1975

In the past the pattern of business down-trend usually appeared in the form of, first, decrease in facility investment, then decrease in inventory level, followed by reduced level of consumption. But the pattern nowadays is becoming just the opposite, that is, first, consumption decrease, then inventory level increase, followed by restriction of facility investment. Also in the past, the greater effort was placed in strengthening of hardware areas through optimization and modernization of production means on the premise of sales. But lately software areas take most of the main effort to establish production mean with sales as its objective. Under these circumstances one of the real problems facing production activities today is the conflicting relationship between sales and production functions. This occurs due to differences of their view points. Then, in order to achieve maximum profit at the least cost, which is the ultimate objective of a production activity, the need arises to effectively coordinate sales demand and plant production capacity. For this purpose strong control means and function must be devised. In our case study example we illustrate a management technique for a combined planning function, of optimal coordination of product mixes utilizing a computerized linear programming model as control means of attaining maximum profit. It is hoped that this example help achieve some of corporate objectives.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.311-314
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• 2001

The objectives of this paper include the development of an agile prototype of SFFS, the $CAFL^{VM}$(Computer Aided fabrication of Lamination for Various Material), which is suitable for the multi-item and small-quantity production and various material fabrication. This paper includes remodeling of the layer slices for the 2D cutting, supplementing information of the layer slices and developing process conditions to fabricate products of various shape. And also includes developing control hardware as well as software by enhancing BOF of the manipulator to 3 degree for the precise 2D cutting. It will generate optimal layer trajectory considering the dynamic characteristics of the laser beam. The system can be used as a competitive agile protype system in terms of various materials, fabrication speed, and accuracy by CAD modeling precise layer slicing, material development, robot path control, and optimization of the support structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.681-684
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• 2008

Bluetooth baseband performs FEC (forward error check) at the interface of transmitter and receiver modem. Well-designed FEC means directly the efficiency of retransmission of the data payload therefore design optimization is very important. In this paper, we designed a optimal 1/3, 2/3 type of FEC. 1/3 FEC. which performs 3 times customary repetition was designed for packet header, and 2/3 FEC was designed for data packets with (15, 10) reduced hamming code. The proposed hardware FEC block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized FEC block operated at 40Mhz normal clock speed of the target baseband microcontroller.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.299-300
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• 1998

Recently the development of medical modality like as MRI, 3D US, DR etc is very active. Therefore it is more required not only the enhancement of quality in medical service but the improvement of medical system based on quantization, minimization, and optimization of high speed. Especially, as the changing into the digital modality system, it gets to start using ASIC(Application Specific Integrated Circuit) to realize one board system. It requires the implementation of hardware debugging and effective speedy algorithm with more speed and accuracy in order to support and replace existing device. If objected image could be linked to high speed process board with special interface and pre-processed using FPGA, it can be used in real time image processing and protocol of HIS(Hospital Information System). This study can support the basic circuit design of medical image board which is able to realize image processing basically using digitalized medical image, and to interface between existing device and image board containing image processing algorithm.