• Tunnel and Underground Space
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• v.19 no.1
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• pp.31-42
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• 2009

One set of hardware system of guide point method (GP method), modified from the multistage convergent photographing technique, was developed to interpret the geometrical characteristics of Joints photogrammetrically on rock slope. Before the field application of the hardware system, the level of errors and constraints that ran be acceptable in the field measurement has been severely investigated in the laboratory and the optimum photographing scheme was analyzed. The range of the most suitable convergence angle between two cameras was $25^{\circ}{\sim}150^{\circ}$ and the photographing distance was about 5.5 m when using a 2 M pixel digital camera. An extended analyzing technique, which was newly developed in this study, was applied to the field measurement to magnify the benefits of GP method. This technique can be applied when survey for the wide range of rock surface is necessary. The global coordinates of ground control points for the neighbor photographing area ran be introduced without any preparation from the previous photographed area using this technique. It could reduce phographing time in the field.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.6
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• pp.765-772
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• 2011

In this research, the fuel cell system model capable of generating codes in real time was developed to construct of a HIL (Hardware-In-the-Loop) for a SOFC-powered ship. Moreover, the effects of the distribution of the exhaust gas flow rates in a stack, the flow rates of fuels and temperature of air supplied on the temperature characteristics of fuels supplied to the cathode and the anode, the output power of the stack and system efficiency are examined to minimize the temperature difference between fuels supplied to the stack used in a 500kW SOFC system using methane as a fuel. As a result, the temperatures of fuels supplied to the cathode and the anode maintain at 830K when the opening factor of three-way valve located at outlet of turbine is 0.839. Also the process for optimization of methane flow rate considering the fuel cell stack and system efficiency is required to increase the temperatures of fuels supplied to the stack.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.8
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• pp.3076-3082
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• 2010

The techniques and the products which use various video compression codec are come out from army or civil field. In existing high-end PC environment, process of the video compression codec does not become a problem, but in embedded system environments which limited system resources, because the system load due to the high-resolution images compressed by high-density, issues of performance and utilization are highlighted. This paper proposes the DirectShow Filter interfaces which are a hardware method in order to solve the problem existing software algorithms for image compression performance and peripheral interfaces.

• Journal of Navigation and Port Research
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• v.40 no.4
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• pp.165-171
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• 2016

SEEMP (Ship Energy Efficiency Management Plan) has entered into force since 2013 for the reduction of GHG emission of operating ships. SEEMP guidelines include the hardware modification or installation of energy-saving device on ship. It also includes software based energy-saving technology such as optimum routing, speed optimization, etc. Hardware based technologies are not easy to apply to ongoing vessel due to the operational restriction. Therefore, IT based energy-saving technology was applied and its energy efficiency was evaluated using before and after energy-saving system applied voyage data. SEEMP advises a voluntary participation of EEOI (Ship Energy Efficiency Operation Indicator) use as an indicator of ship energy efficiency operation, and those results were also shown to evaluate the improvement efficiency of energy-saving system.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.969-976
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• 2019

A lightweight artificial intelligence hardware has made great strides in many application areas. In general, a lightweight artificial intelligence system consist of lightweight artificial intelligence engine and preprocessor including feature selection, generation, extraction, and normalization. In order to achieve optimal performance in broad range of applications, lightweight artificial intelligence system needs to choose a good preprocessing function and set their respective hyper-parameters. This paper proposes a unified framework for a lightweight artificial intelligence system and utilization method for finding models with optimal performance to use on a given dataset. The proposed unified framework can easily generate a model combined with preprocessing functions and lightweight artificial intelligence engine. In performance evaluation using handwritten image dataset and fall detection dataset measured with inertial sensor, the proposed unified framework showed building optimal artificial intelligence models with over 90% test accuracy.

• The Journal of the Acoustical Society of Korea
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• v.25 no.2
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• pp.61-71
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• 2006

An MP3 encoder chip has been designed and fabricated with the hardware and software co-design concepts. In the aspect of the software. the calculation cycles of the distortion control loop. which requires most of the calculation cycles in MP3 encoding procedure. have been reduced to $67\%$ of the original algorithm through the 'scale factor Pre-calculation'. By using a floating Point 32 bit DSP core and designing the FFT block with the hardware. we can get the additional reduction of the calculation cycles in addition to the software optimization. The designed chip has been verified using HW emulation and fabricated via 0.25um CMOS technology The fabricated chip has the size of $6.2{\time}6.2mm^2$ and operates normally on the test board in the qualitative and quantitative aspect.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.3046-3070
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• 2017

Nowadays, the utilization of multiprocessor environments has been increased due to the increase in time complexity of application programs and decrease in hardware costs. In such architectures during the compilation step, each program is decomposed into the smaller and maybe dependent segments so-called tasks. Precedence constraints, required execution times of the tasks, and communication costs among them are modeled using a directed acyclic graph (DAG) named task-graph. All the tasks in the task-graph must be assigned to a predefined number of processors in such a way that the precedence constraints are preserved, and the program's completion time is minimized, and this is an NP-hard problem from the time-complexity point of view. The results obtained by different approaches are dominated by two major factors; first, which order of tasks should be selected (sequence subproblem), and second, how the selected sequence should be assigned to the processors (assigning subproblem). In this paper, a hybrid proposed approach has been presented, in which two different artificial ant colonies cooperate to solve the multiprocessor task-scheduling problem; one colony to tackle the sequence subproblem, and another to cope with assigning subproblem. The utilization of background knowledge about the problem (different priority measurements of the tasks) has made the proposed approach very robust and efficient. 125 different task-graphs with various shape parameters such as size, communication-to-computation ratio and parallelism have been utilized for a comprehensive evaluation of the proposed approach, and the results show its superiority versus the other conventional methods from the performance point of view.

• The Journal of the Korea Contents Association
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• v.9 no.8
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• pp.198-207
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• 2009

Recently, it was possible to represent the realistic clothes in the cloth simulation along with growth of 3D computer animation such as visual contents. In addition, because of the development of H/W(Hardware) and S/W(Software), the accessibility and participation are growing. However, in order to make the image of high quality of 3D animation, the optimized production pipeline was need. In this paper, in order to overcome the limitation of exiting 3D computer animation production pipeline, we propose the optimized production pipeline of the cloth simulation. Our production pipeline makes the optimization arrangement in consideration of the mobility in order to supplement the related structure limit toward each part of the existing pipeline. Moreover, by utilizing the dummy cloth the association nature with the animation part is solved and a performance is improved. The proposal pipeline actually introduced to the animation production. And then we can improve the performance production time and production manpower consumption. Consequently, our pipeline is guaranteed an optimized work by emphasizing a connection in the direct image production.