• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.185-192
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• 2010

This paper presents a hardware-efficient auto-correlation scheme for the synchronization of MIMO-OFDM based wireless local area network (WLAN) systems, such as IEEE 802.11n. Carrier frequency offset (CFO) estimation for the frequency synchronization requires high complexity auto-correlation operations of many training symbols. In order to reduce the hardware complexity of the MIMO-OFDM synchronization, we propose an efficient correlation scheme based on time-multiplexing technique and the use of reduced samples while preserving the performance. Compared to a conventional architecture, the proposed architecture requires only 27% logic gates and 22% power consumption with acceptable BER performance loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3256-3264
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• 1996

This paper presents an efficient VLSI architecture for transposing matris in high speed. In the case of transposing N*N matrix, N$^{2}$ numbers of transposition cells are configured as regular and spuare shaped structure, and pipeline structure for operating each transposition cell in paralle. Transposition cell consists of register and input data selector. The characteristic of this architecture is that the data to be transposed are divided into several bundles of bits, then processed serially. Using the serial transposition of divided input data, hardware complexity of transpositioncell can be reduced, and routing between adjacent transposition cells can be simple. the proposed architecture is designed and implemented with 0.5 .mu.m VLSI library. As a result, it shows stable operation in 200 MHz and less hardware complexity than conventional architectures.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.6
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• pp.2497-2517
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• 2020

For compressed sensing (CS) applications, it is significant to construct deterministic measurement matrices with good practical features, including good sensing performance, low memory cost, low computational complexity and easy hardware implementation. In this paper, a deterministic construction method of bipolar measurement matrices is presented based on binary sequence family (BSF). This method is of interest to be applied for sparse signal restore and image block CS. Coherence is an important tool to describe and compare the performance of various sensing matrices. Lower coherence implies higher reconstruction accuracy. The coherence of proposed measurement matrices is analyzed and derived to be smaller than the corresponding Gaussian and Bernoulli random matrices. Simulation experiments show that the proposed matrices outperform the corresponding Gaussian, Bernoulli, binary and chaotic bipolar matrices in reconstruction accuracy. Meanwhile, the proposed matrices can reduce the reconstruction time compared with their Gaussian counterpart. Moreover, the proposed matrices are very efficient for sensing performance, memory, complexity and hardware realization, which is beneficial to practical CS.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.69-72
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• 1999

In this paper, an efficient time domain equalization algorithm for discrete wavelet multitone(DWMT) data transmission is developed. In this algorithm, the time domain equalizer(TEQ) consists of two stages, i.e., the channel impulse response shortening equalizer(TEQ-S) in the first stage and the channel frequency flattening equalizer(TEQ-F) in the second stage. TEQ-S reduces the length of transmission channel impulse response to decrease intersymbol interference(ISI) followed by TEQ-F that enhances the channel frequency response characteristics to the level of an ideal channel, hence diminishes the bit error rate. TEQ-S is implemented using the least-squares(LS) method, while TEQ-F is designed by using the least mean-square(LMS) algorithm. Since DWMT system also requires of the frequency domain equalizer in order to further reduce ICI and ISI the hardware complexity is an another concern. However, by adopting an well designed and trained TEQ, the hardware complexity of the whole DWMT system can be greatly reduced.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.2
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• pp.185-192
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• 2002

A novel GPS initial synchronization scheme with low hardware complexity is proposed. The proposed method has the decomposed differential matched filter, which consists of 25% multiplier and adder of the conventional matched filter. This paper presents the generalized mean acquisition time of initial synchronization scheme with multiple correlator. It is shown that the proposed method, in spite of its low hardware complexity, has the equal performance to the conventional method. The performance of the proposed method is verified through the simulation test by the GPS simulator. It is shown that the proposed method prevents the squaring loss of non-coherent integration.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.89-92
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• 2004

An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a modified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the one third as many as the one that is implemented with the NLMS algorithm, without so much degradation of performances.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1540-1547
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• 2000

In this paper, the performance of the MMSE multiuser detector is compared with the conventional detector with respect to the signal-to-noise ratio, the number of users and the Nakagami parameter under AWGN as well as Nakagami fading channel. The results show that the MMSE multiuser detector is superior to the conventional detector with respect to cancelling the multiple access interference. However, its drawback is the hardware's complexity. To solve this drawback, the advanced MMSE multiuser detector is presented, and its performance is analyzed. The number of taps in the advanced MMSE multiuser are independent of the processing gain. Thus, the system engineer can choose the appropriate number of taps in the detector to achieve a optimal trade-off between the hardware complexity and the performance of system.

• ETRI Journal
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• v.43 no.2
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• pp.197-208
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• 2021

Single-carrier frequency division multiple access (SC-FDMA) is currently being used in long-term evolution uplink communications owing to its low peak-to-average power ratio (PAPR). This study proposes a new transceiver design for an SC-FDMA system based on Walsh-Hadamard transform (WHT). The proposed WHT-based SC-FDMA system has low-PAPR and better bit-error rate (BER) performance compared with the conventional SC-FDMA system. The WHT-based SC-FDMA transmitter has the same complexity as that of discrete Fourier transform (DFT)-based transmitter, while the receiver's complexity is higher than that of the DFT-based receiver. The exponential companding technique is used to reduce its PAPR without degrading its BER. Moreover, the performances of different ordered WHT systems have been studied in additive white Gaussian noise and multipath fading environments. The proposed system has been verified experimentally by considering a real-time channel with the help of wireless open-access research platform hardware. The supremacy of the proposed transceiver is demonstrated based on simulated and experimental results.