• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1737-1744
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• 2010

The Image sensor needs various image processing to improve image quality. ISP(Image Signal Processor) performs various image processing. Conventional vision cameras have own software ISP functions and perform in PC instead of using commercial ISP chips. However these methods have problems such as large computation for image processing. In this paper, we proposed ISP that significantly reduced chip area by efficient sharing of hardware and software. Large operation blocks are designed to hardware for high performances, and we used hardware simultaneously with software considering the size of the hardware. The implemented ISP can process VGA(640*4800) images and has 91450 gate sizes in 0.35um process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.185-196
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• 2009

SCA is proposed in order to operate various wireless systems in the single terminal platforms and uses the CORBA middleware to guarantee the platform-independence for software components. As the reconstruction demand is expanded in the software component to the logic level to many reasons, CORBA has to guarantee the independence of hardware on board. Accordingly. the characteristics depending on hardware board is ed. And the IDL-based interworking interface about the component has to be provided. In this paper, we described about local transport for guaranteeing the independency on the hardware board and the HAO Core for providing a coupling by the CORBA IDL identically with the other component. HAO produced at 2,900 logic cell size in average and provided the performance of the tens times than the software component. Through the use of HAO in the SCA-based development environment, it was naturally expanded to not only the software area but also the FPGA logic.

• Journal of KIISE:Software and Applications
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• v.33 no.11
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• pp.915-922
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• 2006

Recently, the requirements of the embedded software are getting diverse as the diversity of embedded software application fields increases. The systematic development methods are issued to deal with the dependency between hardware and software. However, the existing development methods have not considered the software's close connection to hardware and the high-level reusability for common requirements of several similar domains. In this paper, we propose a design method of development process model of product lines to support an efficient development method for embedded software. For this, we firstly suggest a domain scoping method and an IDEF0(Integration DEFinition)-based business model for extracting the efficient requirements. Next, we present a component deriving method based on the service architecture and an architecture design method after considering the hardware dependency. And we explain the artifacts of MSDFS(Multi Sensor Data Fusion System) at each design step in order to show how the proposed model can be applied to the embedded software development.

• Electronics and Telecommunications Trends
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• v.33 no.2
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• pp.10-21
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• 2018

Software defined technology (SDx), which defines the IT infrastructure based on software and controls that are not dependent on a specific hardware, and provides a rapid and flexible IT infrastructure, is increasing. SDx features centralized control, a common commercial product infrastructure, hardware-software dualization, and programmability. With the advent of the fourth industrial revolution, in which various application services are emerging based on IT infrastructure, interest in SDx is gradually increasing as the need for infrastructure flexibility and an agile business environment is increasing. This paper reviews the market trends of software defined anything using SDx and the trends of major vendors.

• Journal of the Korean Society for Railway
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• v.9 no.5 s.36
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• pp.601-605
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• 2006

Reliability of the Railway signaling system which is safety critical is determined by reliability of hardware and software. Reliability of hardware is easily predicted and demonstrated through lots of different studies and environmental tests, while that of software is estimated by the iterative test outcomes so estimates of reliability will depend on the inputs. Combinations of inputs to and outputs from the software may be mostly combinatoric and therefore all the combinations could not be tested. As a result, it has been more important to calculate reliability by means of a simpler method. This paper identifies the reliability prediction equation applicable to reliability prediction for railway signaling system software, and performs the simulation of onboard equipment of automatic train control for high speed train to review reliability prediction and validity.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.405-414
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• 2012

In this paper, we propose a reliability estimation method for DI&C systems. At the system level, a fault tree model is suggested and Boolean algebra is used to obtain the minimal cut sets. At the component level, an exponential distribution is used to model hardware failures, and Bayesian estimation is suggested to estimate the failure rate. Additionally, a binomial distribution is used to model software failures, and a recently developed software reliability estimation method is suggested to estimate the software failure rate. The overall system reliability is then estimated based on minimal cut sets, hardware failure rates and software failure rates.

• Journal of Digital Contents Society
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• v.5 no.1
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• pp.61-65
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• 2004

This paper presents a method of constructing the embedded systems based on hardware/software co-design approach that was key methodology. The proposed method was important technology enable to implement advanced multimedia systems and digital contents creating that are rapidly growing of the new information technology.

• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.257-266
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• 2006

Recently TCP/IP Offload Engine (TOE) technology, which processes TCP/IP on a network adapter instead of the host CPU, has become an important approach to reduce TCP/IP processing overhead in the host CPU. There have been two approaches to implementing TOE: software TOE, in which TCP/IP is processed by an embedded processor on a network adapter; and hardware TOE, in which all TCP/IP functions are implemented by hardware. This paper proposes a hybrid TOE that combines software and hardware functions in the TOE. In the hybrid TOE, functions that cannot have guaranteed performance on an embedded processor because of heavy load are implemented by hardware. Other functions that do not impose as much load are implemented by software on embedded processors. The hybrid TOE guarantees network performance near that of hardware TOE and it has the advantage of flexibility, because it is easy to add new functions or offload upper-level protocols of TCP/IP. In this paper, we developed a prototype board with an FPGA and an ARM processor to implement a hybrid TOE prototype. We implemented the hardware modules on the FPGA and the software modules on the ARM processor. We also developed a coprocessing mechanism between the hardware and software modules. Experimental results proved that the hybrid TOE prototype can greatly reduce the load on a host CPU and we analyzed the effects of the coprocessing mechanism. Finally, we analyzed important features that are required to implement a complete hybrid TOE and we predict its performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2232-2239
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• 2016

IoT industry has been highlighted in the domestic and foreign country. Since most IoT systems operate separate servers in Internet to control IoT hardwares, there exists the possibility of security problems. Also, IoT systems in markets use their own hardware controllers and devices. As a result, there are many limitations in adding new sensors or devices and using applications to access hardware controllers. To solve these problems, we have developed a novel IoT hardware control system based on a mobile messenger. For the security, we have adopted a secure mobile messenger, Telegram, which has its own security protection. Also, it can improve the easy of the usage without any installation of specific applications. For the enhancement of the system accessibility, the proposed IoT system supports various network protocols. As a result, there are many possibility to include various functions in the system. Finally, our IoT system can analyze the collected information from sensors to provide useful information to the users. Through the experiment, we show that the proposed IoT system can perform well.