• Title/Summary/Keyword: halo doping

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Scaling theory to minimize the roll-off of threshold voltage for ultra fine MOSFET (미세 구조 MOSFET에서 문턱전압 변화를 최소화하기 위한 최적의 스켈링 이론)

  • 정학기;김재홍;고석웅
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.4
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    • pp.719-724
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    • 2003
  • In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model (QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll off characteristics for threshold voltage of MOSFET with decreasing channel length, we know $\alpha$ value must be nearly 1 in the generalized scaling.

Analysis of the Drain Current in Nonuniformly Doped Channel(NUDC) MOSFET's due to Pocket Ion Implantation (포켓 이온주입으로 비균질 채널도핑을 갖는 MOSFET소자의 드레인 전류 해석)

  • Koo, Hoe-Woo;Park, Joo-Seog;Lee, Kie-Young
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.9
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    • pp.21-30
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    • 1999
  • Halo pocket implantation in MOSFETs, which is known to be an efficient method to provent the punchthrough and threshold voltage roll-off phenomena, decreases the drain current of MOSFET devices. Although the decrease of the drain current in halo structure MOSFET is usually explained in terms of the increase of the threshold voltage, more decrease in the drain current than is predicted by the increased threshold voltage has experimentally been observed. In this work, the effect of halo doping profile on the drain current degradation is investigated in terms of the field distribution along the channel. Effective mobility model of the halo MOSFETs due to pocket implantation is presented and the degradation of the mobility is shown to be effective in the further decrease of the drain current. Present model is shown to be in good agreement with experimental results.

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A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

  • Sahu, P.K.;Mohapatra, S.K.;Pradhan, K.P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.647-654
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    • 2013
  • The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

Scaling theory to minimize the roll-off of threshold voltage for nano scale MOSFET (나노 구조 MOSFET의 문턱전압 변화를 최소화하기 위한 스케일링 이론)

  • 김영동;김재홍;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.494-497
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    • 2002
  • In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model(QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know u value must be nearly 1 in the generalized scaling.

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Gate Workfunction Optimization of a 32 nm Metal Gate MOSFET for Low Power Applications (저전력 분야 응용을 위한 32nm 금속 게이트 전극 MOSFET 소자의 게이트 workfunction 의 최적화)

  • Oh, Yong-Ho;Kim, Young-Min
    • Proceedings of the KIEE Conference
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    • 2005.07c
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    • pp.1974-1976
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    • 2005
  • The feasibility of a midgap metal gate is investigated for 32nm MOSFET low power applications. The midgap metal gate MOSFET is found to deliver a driving current as high as a bandedge gate one for the low power applications if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in ITRS roadmap. In addition, a process simulation is run using halo implants and thermal processes to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. From the thermal budget point of view, the bandedge metal gate MOSFET is more vulnerable to the following thermal process than the midgap metal gate MOSFET since it requires a steeper retrograde doping profile. Based on the results, a guideline for the gate workfunction and the channel profile in the 32 nm MOSFET is proposed.

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