• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3C
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• pp.256-262
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• 2002

This paper presents a novel radix-4 modular multiplication algorithm based on the sign estimation technique (3). The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance modular multiplication of large numbers. Our algorithm requires only (n/2+3) clock cycle for n bit modulus in performing modular multiplication. Our algorithm out-performs existing algorithm in terms of required clock cycles by a half, It is efficient for modular exponentiation with large modulus used in RSA cryptosystem. Also, we use high-speed adder (7) instead of CPA (Carry Propagation Adder) for modular multiplication hardware performance in fecal stage of CSA (Carry Save Adder) output. We apply RL (Right-and-Left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, One 1024-bit RSA operation can be done after n(n/2+3) clock cycles.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.53-53
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• 2003

• Journal of Applied and Pure Mathematics
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• v.5 no.3_4
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• pp.187-196
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• 2023

This study is about spin half add operations in 𝓑₂ and 𝓑₃. The burden of technological structures has increased due to the increase in the use of today's technological applications or the processes in the digital systems used. This has increased the importance of fast transactions and storage areas. For this, less transactions, more gain and storage space are foreseen. We have handle tit (triple digit) system instead of bit (binary digit). 729 is reached in 3⁶ in 𝓑₃ while 256 is reached with 2⁸ in 𝓑₂. The volume and number of transactions are shortened in 𝓑₃. The limited storage space at the maximum level is storaged. The logic connectors and the complement of an element in 𝓑₂ and the course of the connectors and the complements of the elements in 𝓑₃ are examined. "Carry" calculations in calculating addition and "borrow" in calculating difference are given in 𝓑₃. The logic structure 𝓑₂ is seen to embedded in the logic structure 𝓑₃. This situation enriches the logic structure. Some theorems and lemmas and properties in logic structure 𝓑₂ are extended to logic structure 𝓑₃.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• Proceedings of the Optical Society of Korea Conference
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• 2001.02a
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• pp.74-75
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• 2001

현재의 통신망에서는 clock recovery, regeneration 등을 전기적으로 처리하고 있으나 처리속도의 한계가 있고, 미래의 초고속 네트웍은 이러한 전기적 신호처리의 속도한계를 극복하는 기술이 필요하다. 그러므로, 고속의 광교환과 광신호처리 등 광신호를 전기적으로 바꾸거나 제어하지 않고 전광으로 처리하는 기술에 대한 연구가 진행되고 있으며 이러한 전광신호 처리에 고속의 전광 논리소자가 요구된다. 초기의 전광 논리소자 연구에서는 AND, OR, NOR, XOR 등의 기본 논리 기능이 주로 구현되었으며 이를 활용하여 Shift Register, Binary counter, 전광 반가산기, 직/병렬 데이터 변환기와 같은 복합기능 논리소자의 구현 연구가 이루어지고 있다. (중략)

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.33-44
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• 2008

The efficiency of pairing based cryptosystems depends on the computation of pairings. pairings is defined over finite fileds GF$(3^m)$ by trinomials due to efficiency. The hardware architectures for pairings have been widely studied. This paper proposes new adder and multiplier for GF(3) which are more efficient than previous results. Furthermore, this paper proposes a new unified adder-subtractor for GF$(3^m)$ based on the proposed adder and multiplier. Finally, this paper proposes new multiplier for GF$(3^m)$. The proposed MSB-first bit-serial multiplier for GF$(p^m)$ reduces the time delay by approximately 30 % and the size of register by half than previous LSB-first multipliers. The proposed multiplier can be applied to all finite fields defined by trinomials.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.693-696
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• 1999

This paper describes a new voltage recorder for the voltage management of a power distribution line by using a new voltage measurement technique. The RMS(Root Mean Square) voltage measurement for the power line under the assumption of a sinusoidal input voltage is taken by the full-wave rectifier, half-adder utilizing operational amplifier(OP) circuit. A/D converter utilizing a dual slope converter converts an analog voltage signal into a serial pulse. The pulse is counted with a single chip micro-controller, converted with the RMS voltage, and saved into a flash memory. In the last, a new voltage recorder with compact size and multifunction is developed. Also, Voltage Management System that can analyze the stored data via RS-232C cable is developed based on Windows 95 and Visual C++.