• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.355-361
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• 1987

The shuffle-exchange graph is known as a structure to perform the parallel algorithms like Discrete Fourier Transform(DFT), matrix multiplication and sorting. In this paper, the layout for the shuffle-exchange graph is described and this layout places emphasis on the placement of nodes that has the capability to have as small area as possible, have as a small number of crossings as possible, and have as short wires as possible. The algorithm corrdsponding these conditions is proposed and each evaluation factor and the placement of the N-node shuffle-exchange graph is performed with FORTRAN and BASIC program, and these results are calcualted.

• Journal of KIISE:Software and Applications
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• v.36 no.11
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• pp.875-890
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• 2009

Metabolimics interprets an organism as a network of functional units and an organism is represented by a metabolic pathway i.e., well-displayed graph. So a software tool for drawing pathway is necessary to understand it comprehensively. These tools have a problem that edge-crossings exponentially increase as the number of nodes grows. To apply automatic graph layout techniques to the genome-scale metabolic flow, it is very important to reduce unnecessary edge-crossing on a metabolic pathway layout. In this paper, we design and implement 2.5D metabolic pathway layout modules. Metabolic pathways are represented hierarchically by making use of the '2-layered layout algorithm' in 3D. It enhances the readability and reduces unnecessary edge-crossings by using 3D layout modules instead of 2D layout algorithms.

• Journal of the HCI Society of Korea
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• v.10 no.1
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• pp.5-17
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• 2015

Nowadays various public data have been serviced to the public. Through the opening of public data, the transparency and effectiveness of public policy developed by governments are increased and users can lead to the growth of industry related to public data. Since end-users of using public data are citizens, it is very important for everyone to figure out the meaning of public data using proper visualization techniques. In this work, to indicate the significance of widespread public data, we consider UN voting record as public data in which many people may be interested. In general, it has high utilization value by diplomatic and educational purposes, and is available in public. If we use proper data mining and visualization algorithms, we can get an insight regarding the voting patterns of UN members. To visualize, it is necessary to measure the voting similarity values among UN members and then a social graph is created by the similarity values. Next, using a graph layout algorithm, the social graph is rendered on the screen. If we use the existing method for visualizing the social graph, it is hard to understand the meaning of the social graph because the graph is usually dense. To improve the weak point of the existing social graph visualization, we propose Friend-Matching, Friend-Rival Matching, and Bubble Heap algorithms in this paper. We also validate that our proposed algorithms can improve the quality of visualizing social graphs displayed by the existing method. Finally, our prototype system has been released in http://datalab.kunsan.ac.kr/politiz/un/. Please, see if it is useful in the aspect of public data utilization.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.202-213
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• 2007

A network is an important model widely used in natural and social science as well as engineering. To analyze these networks easily it is necessary that we should layout the features of networks visually. These Graph-Layout researches have been performed recently according to the development of the computer technology. Among them, the Scale-free Network that stands out in these days is widely used in analyzing and understanding the complicated situations in various fields. The Scale-free Network is featured in two points. The first, the number of link(Degree) shows the Power-function distribution. The second, the network has the hub that has multiple links. Consequently, it is important for us to represent the hub visually in Scale-free Network but the existing Graph-layout algorithms only represent clusters for the present. Therefor in this thesis we suggest Graph-layout algorithm that effectively presents the Scale-free network. The Hubity(hub+ity) repulsive force between hubs in suggested algorithm in this thesis is in inverse proportion to the distance, and if the degree of hubs increases in a times the Hubity repulsive force between hubs is ${\alpha}^{\gamma}$ times (${\gamma}$??is a connection line index). Also, if the algorithm has the counter that controls the force in proportion to the total node number and the total link number, The Hubity repulsive force is independent of the scale of a network. The proposed algorithm is compared with Graph-layout algorithm through an experiment. The experimental process is as follows: First of all, make out the hub that exists in the network or not. Check out the connection line index to recognize the existence of hub, and then if the value of connection line index is between 2 and 3, then conclude the Scale-free network that has a hub. And then use the suggested algorithm. In result, We validated that the proposed Graph-layout algorithm showed the Scale-free network more effectively than the existing cluster-centered algorithms[Noack, etc.].

• Genomics & Informatics
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• v.4 no.3
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• pp.118-124
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• 2006

For the direct understanding of flow, pathway data are usually represented as directed graphs in biological journals and texts. Databases of metabolic pathways or signal transduction pathways inevitably contain these kinds of graphs to show the flow. KEGG, one of the representative pathway databases, uses the manually drawn figure which can not be easily maintained. Graph layout algorithms are applied for visualizing metabolic pathways in some databases, such as EcoCyc. Although these can express any changes of data in the real time, it exponentially increases the edge crossings according to the increase of nodes. For the understanding of genome scale flow of metabolism, it is very important to reduce the unnecessary edge crossings which exist in the automatic graph layout. We propose a metabolic pathway drawing algorithm for reducing the number of edge crossings by considering the fact that metabolic pathway graph is scale-free network. The experimental results show that the number of edge crossings is reduced about $37{\sim}40%$ by the consideration of scale-free network in contrast with non-considering scale-free network. And also we found that the increase of nodes do not always mean that there is an increase of edge crossings.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.27 no.2
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• pp.68-77
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• 2004

This paper considers the workforce assignment problem to minimize both the deviations of workloads assigned to workers and to maximize the total preference between each worker and each machine. Because of the high expense of technology education and the difficulties of firing employees, there is no part time workers in semiconductor industry. Therefore, multi-skilled workers are trained for performing various operations in several machines. The bicriteria workforce assignment problem in this paper is not easy to obtain the optimal solution considering the aisle structure and it is belong to NP-class. The proposed heuristic algorithms are developed based on the combination of spacefilling curve technique, simulated annealing technique and graph theory focusing on the multiple-row machine layout. Examples are presented for the proposed algorithms how to find a good solution.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.40-45
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• 2018

With the advent of big data and social networks, large-scale graph processing becomes popular research topic. Recently, an optimization technique called Gorder has been proposed to improve the performance of in-memory graph processing. This technique improves performance by optimizing the graph layout on memory to have better cache locality. However, since it is designed for in-memory graph processing systems, the technique is not suitable for disk-based graph engines; also the cost for applying the technique is significantly high. To solve the problem, we propose a new graph ordering called I/O Order. I/O Order considers the characteristics of I/O accesses for SSDs and HDDs to improve the performance of disk-based graph engine. In addition, the algorithmic complexity of I/O Order is simple compared to Gorder, hence it is cheaper to apply I/O Ordering. I/O order reduces the cost of pre-processing up to 9.6 times compared to that of Gorder's, still its performance is 2 times higher compared to the Random in low-locality graph algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.228-234
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• 2006

This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.712-720
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• 2001

Algorithms from the research of the layout migration were proposed in the paper. These are automatic recognition algorithm for the VLSI devices from it, graph based construction algorithm to maintain the constraints, dependencies, and design rule between the devices, and high speed compaction algorithm to reduce size of the VLSI area and reuse the design with compacted size for the new technology. Also, this paper describes that why proposed algorithms are essential for the era of the SoC (System on a Chip), design reuse, and IP DB, which are the big concerns in these days. In addition to introduce our algorithms, the benchmark showed that our performance is superior by 27 times faster than that of the commercial one, and has better efficiency by 3 times in disk usage.