• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1833-1835
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• 1999

게이트 산화막의 breakdown 전압을 나추기 위해 질소 주입을 하는 과정은 실리콘층에 패드 산화막을 성장시킨 후 실리콘과 패드 산화막 층사이에 질소 이온을 주입하였다. 이온 주입 후 패드 산화막 층을 제거하고 그 위에 게이트 산화막 층을 성장시키는 방법을 사용하였다. 이러한 방법을 질소 이온의 농도를 변화시키면서 여러번 반복하였다 그래서 질소 이온 농도의 변화에 따른 게이트 산화막 두께의 변화를 측정하였다. 그 결과 질소 농도이 따른 게이트 산화막 성장비율을 알아 보았다. 그리고 질소 농도의 변화에 따른 Breakdown 전압과 누설 전류의 변화를 측정하였다. 또한 앞에서 말한 질소 주입 공정이 들어가면서 추가적으로 발생하는 과정에 대해 고찰하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.1-4
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• 1998

In this paper, we have studied a variation of I-V characteristics, and time-dependent dielectric breakdown(TDDB) of thin layer NO and ONO film depending on nitridation and reoxidation time, respectively, and measured a variation of leakage current and charge-to-breakdown(Q$\_$bd/) of optimized NO and ONO film depending on ambient temperature, and then compared with the properties of conventional SiO$_2$. From the results, we find that these NO and ONO thin films are strongly influenced by process time and the optimized ONO film shows superior dielectric characteristics, and Q$\_$bd/ performance over the NO film and SiO$_2$, while maintaining a similar electric field dependence compared with NO layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.546-550
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• 2001

A new Lateral Trench Insulated Gate Bipolar Transistor(LTIGBT) with p$^{+}$ diverter was proposed to improve the characteristics of the conventional LTIGBT. The forward blocking voltage of the proposed LTIGBT with p$^{+}$ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p$^{+}$ diverter region of the proposed device was enclosed trench oxide layer, he electric field moved toward trench-oxide layer, and punch through breakdown of LTIGBT with p$^{+}$ diverter was occurred, lately. Therefore, the p$^{+}$ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. The Latch-up current densities of the conventional LTIGBT and proposed LTIGBT were 540A/$\textrm{cm}^2$, and 1453A/$\textrm{cm}^2$, respectively. The enhanced latch-up capability of the proposed LTIGBT was obtained through holes in the current directly reaching the cathode via the p$^{+}$ divert region and p$^{+}$ cathode layer beneath n$^{+}$ cathode layer./ cathode layer.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.84-87
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• 2010

We manufacture an antifuse OTP (One-time programmable) cell for analog trimming which will be used in power management ICs. For the antifuse cell using dual program voltage of VPP (=7V) and VNN (=-5V), the thin gate oxide is broken down by applying a voltage higher than the hard break-down voltage to the terminals of the antifuse. The area of the manufactured antifuse OTP cell using $0.18{\mu}m$ BCD process is $48.01{\mu}m^2$ and is about 44.6 percent of that of an eFuse cell. The post-program resistances of the antifuse are good with the values under several kilo ohms when we measure twenty test patterns.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.103-110
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• 1995

Trench-Gate SOI LIGBT with improved latch-up capability has been proposed and verified by MEDICI simulation. The new SOI LIGBT exhibits 6 time larger latch-up capability of the new device is almost preserved independent of lifetime. the large latch-up capability of the new SOI LIGBT may be realized due to the fact that the hole current in the new device would bypass through the shorted cathode contact without passing the p-well region under the n+ cathode. Forward voltage drop is increased by 25% when a epi thickness is 6$\mu$m. However, the increase of the forward voltage is negligible when the epi thickness is increased to 10$\mu$m. It is found that the swithcing time of the new device is almost equal to the conventional devices. Evaluated breakdown voltage of proposed SOILIGBT is 250 V and that of the conventional SOI LIGBT is 240 V, where the thickness of the vuried oxide and n- epi is 3$\mu$m and 6$\mu$m, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.713-717
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• 2011

This paper was carried out design of 600 V GaN power MOSFET Modeling. We decided trench gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 600 V breankdown voltage and $0.4\;m{\Omega}cm^2ultra$ low on resistance. At the same time, we carried out field ring simulation for obtaining high voltage.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.724-728
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• 2002

Inductively-coupled $N_2$O plasma was utilized to grow silicon dioxide at low temperature and applied to fabricate polycrystalline-silicon thin film transistors. At $400^{\circ}C$, the thickness of oxide was limited to 5nm and the oxide contained Si≡N and ≡Si-N-Si≡ bonds. The nitrogen incorporation improved breakdown field to 10MV/cm and reduced the interface charge density to $1.52$\times$10^{11}$ $cm^2$ with negative charge. The $N_2$O plasma gate oxide enhanced the field effect mobility of polycrystalline thin film transistor, compared to $O_2$ plasma gate oxide, due to the reduced interface charge at the $Si/SiO_2$ interface and also due to the reduced trap density at Si grain boundaries by nitrogen passivation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.