• 제목/요약/키워드: gate switching

검색결과 392건 처리시간 0.033초

수소 도핑효과에 의한 ZnO 맴트랜지스터 소자특성 (Resistive Switching Characteristic of ZnO Memtransistor Device by a Proton Doping Effect)

  • 손기훈;강경문;박형호;이홍섭
    • 마이크로전자및패키징학회지
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    • 제27권1호
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    • pp.31-35
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    • 2020
  • 원자층 증착법(ALD: atomic layer deposition)으로 성장된 ZnO n-type 산화물반도체를 이용하여 three terminal memristor (memtransistor) 소자를 제작하여 습도에 따른 그 특성을 관찰하였다. 40 nm 두께의 ZnO 박막을 이용하여 channel width 70 ㎛, length 5 ㎛, back gate 구조의 memtransistor 소자를 제작하여 습도에 (40%, 50%, 60%, 70%) 따른 gate tunable memristive 특성변화를 관찰하였다. 습도가 높아질수록 electron mobility와 gate controllability가 감소하여 수소도핑효과에 의한 carrier 농도가 증가하는 거동의 output curve가 관찰되었다. 60%, 70%의 습도에서 memristive 거동이 관찰되었으며 습도가 높아질수록 on/off ratio는 증가하는 반면 gate controllability가 감소하였다. 60% 습도에서 가장 우수한 특성의 gate tunable memristive 특성을 얻을 수 있었다.

SI-Thyristor의 내부 임피던스 계산을 통한 최적 스위칭 제어 (Optimal switching method of SI-Thyristor using internal impedance evaluation)

  • 주흥진;김봉석;황휘동;박정호;고광철
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.122-122
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    • 2010
  • A Static Induction Thyristor (SI-Thyristor) has a great potential as power semiconductor switch for pulsed power or high voltage applications with fast turn-on switching time and high switching stress endurance (di/dt, dV/dt). However, due to direct commutation between gate driver and SI-Thyristor, it is difficult to design optimal gate driver at the aspect of impedance matching for fast gate current driving into internal SI-Thyristor. Thus, to penetrate fast positive gate current into steady off state of the SI-Thyristor, it is proposed and proceeded the internal impedance calculation of the SI-Thyristor at steady off state with the gate driver while switching conditions that are indicated applied gate voltage, $V_{GK}$ and applied high voltage across anode and cathode, $V_{AK}$.

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스위칭 네트워크와 디지털 접선 장치에서의 CMOS 게이트 어레이 IC 적용 (An Application of CMOS Gate Array Integrated Circuits to Switching Network and Digital Line Concentrator)

  • 박항구;박권철;조용현
    • 대한전자공학회논문지
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    • 제24권4호
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    • pp.652-657
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    • 1987
  • This paper describes an application of CMOS Gate Array Integrated Cricuits to the implementation of three functional units: A Multiplexer, Time Switch, and Demultiplexer in the Switching Network and Digital Line Concentrator of TDX-1 system, which is a fully digital time division electronic switching system in Korea. The application of CMOS Gate Array Integrated Circuits significantly improves the overall system performance in terms of power consumption, cost, size, reliability, and timing margin, etc.

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Improved Circuit Model for Simulating IGBT Switching Transients in VSCs

  • Haleem, Naushath Mohamed;Rajapakse, Athula D.;Gole, Aniruddha M.
    • Journal of Power Electronics
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    • 제18권6호
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    • pp.1901-1911
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    • 2018
  • This study presents a circuit model for simulating the switching transients of insulated-gate bipolar transistors (IGBTs) with inductive load switching. The modeling approach used in this study considers the behavior of IGBTs and freewheeling diodes during the transient process and ignores the complex semiconductor physics-based relationships and parameters. The proposed circuit model can accurately simulate the switching behavior due to the detailed consideration of device-circuit interactions and the nonlinear nature of model parameters, such as internal capacitances. The developed model is incorporated in an IGBT loss calculation module of an electromagnetic transient simulation program to enable the estimation of switching losses in voltage source converters embedded in large power systems.

Gate 전하를 감소시키기 위해 Separate Gate Technique을 이용한 Trench Power MOSFET (Trench Power MOSFET using Separate Gate Technique for Reducing Gate Charge)

  • 조두형;김광수
    • 전기전자학회논문지
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    • 제16권4호
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    • pp.283-289
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    • 2012
  • 이 논문에서 Trench Power MOSFET의 스위칭 성능을 향상시키기 위한 Separate Gate Technique(SGT)을 제안하였다. Trench Power MOSFET의 스위칭 성능을 개선시키기 위해서는 낮은 gate-to-drain 전하 (Miller 전하)가 요구된다. 이를 위하여 제안된 separate gate technique은 얇은(~500A)의 poly-si을 deposition하여 sidewall을 형성함으로서, 기존의 Trench MOSFET에 비해 얇은 gate를 형성하였다. 이 효과로 gate와 drain에 overlap 되는 면적을 줄일 수 있어 gate bottom에 쌓이는 Qgd를 감소시키는 효과를 얻었고, 이에 따른 전기적인 특성을 Silvaco T-CAD silmulation tool을 이용하여 일반적인 Trench MOSFET과 성능을 비교하였다. 그 결과 Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) 및 Crss(reverse recovery capacitance : Cgd) 모두 개선되었으며, 각각 14.3%, 23%, 30%의 capacitance 감소 효과를 확인하였다. 또한 inverter circuit을 구성하여, Qgd와 capacitance 감소로 인한 24%의 reverse recovery time의 성능향상을 확인하였다. 또한 제안된 소자는 기존 소자와 비교하여 어떠한 전기적 특성저하 없이 공정이 가능하다.

1,200V 급 Trench Gate Field stop IGBT 공정변수에 따른 스위칭 특성 연구 (A Study on Switching Characteristics of 1,200V Trench Gate Field stop IGBT Process Variables)

  • 조창현;김대희;안병섭;강이구
    • 전기전자학회논문지
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    • 제25권2호
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    • pp.350-355
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    • 2021
  • IGBT는 MOSFET과 BJT의 구조를 동시에 포함하고 있는 전력반도체 소자이며, MOSFET의 빠른 스위칭 속도와 BJT의 고 내압, 높은 전류내량 특성을 갖고 있다. GBT는 높은 항복전압, 낮은 VCE-SAT, 빠른 스위칭 속도, 고 신뢰성의 이상적인 파워 반도체 소자의 요구사항을 목표로 하는 소자이다. 본 논문에서는 1,200V 급 Trench Gate Field Stop IGBT의 상단 공정 파라미터인 Gate oxide thickness, Trench Gate Width, P+ Emitter width를 변화시키면서 변화하는 Eoff, VCE-SAT을 분석하였고, 이에 따른 최적의 상단 공정 파라미터를 제시하였다. Synopsys T-CAD Simulator를 통해 항복전압 1,470V와 VCE-SAT 2.17V, Eon 0.361mJ, Eoff 1.152mJ의 전기적 특성을 갖는 IGBT 소자를 구현하였다.

MOS-GTO의 스위칭 특성과 Gate Drive 회로 설계에 관한 연구 (A study on the switching character of MOS-GTO and the design of gate drive circuit)

  • 노진입;성세진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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    • pp.231-233
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    • 1991
  • This paper discribes a study on the switching character of MOS-GTO and the design of gate drive circuit. Chopping power supply converter, synchronious and asyncronious motor speed adjustment, inverter, etc., needs low drive energy "high frequency" switches. To fulfill these need, switches must have rapid switching time and insulated gate control. MOS-GTO structure is well suited to these constraints. The power switch is serial installation of a GTO thyrister and a MOS Transistor. The gate of the GTO is linked to positive pole of the cascode structure via a MOS high voltage transistor and ground via a transient absorber diode. This high performance MOS-GTO assembly considerably increases the strength which facilitate the drive of GTO thyristers.

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Synchronous Carrier-based Pulse Width Modulation Switching Method for Vienna Rectifier

  • Park, Jin-Hyuk;Yang, SongHee;Lee, Kyo-Beum
    • Journal of Power Electronics
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    • 제18권2호
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    • pp.604-614
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    • 2018
  • This paper proposes a synchronous switching technique for a Vienna rectifier that uses carrier-based pulse width modulation (CB-PWM). A three-phase Vienna rectifier, similar to a three-level T-type converter with three back-to-back switches, is used as a PWM rectifier. Conventional CB-PWM requires six independent gate signals to operate back-to-back switches. When internal switches are operated synchronously, only three independent gate signals are required, which simplifies the construction of gate driver circuits. However, with this method, total harmonic distortion of the input current is higher than that with conventional CB-PWM switching. A reactive current injection technique is proposed to improve current distortion. The performance of the proposed synchronous switching method and the effectiveness of the reactive current injection technique are verified using simulations and experiments performed with a set of Vienna rectifiers rated at 5 kW.

Switching Characteristics of Amorphous GeSe TFT for Switching Device Application

  • 남기현;김장한;조원주;정홍배
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.403-404
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    • 2012
  • We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

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Electrical Switching Characteristics of Thin Film Transistor with Amorphous Chalcogenide Channel

  • 남기현;김장한;정홍배
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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    • pp.280-281
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    • 2011
  • We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

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