• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.413-417
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• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.9
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• pp.707-711
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• 2013

Carbon nanotubes(CNT) has strength and chemical stability, greatly conductivity characteristics. In particular, MWCNT (multi-walled carbon nanotubes) show rapidly resistance sensitive for changes in the ambient gas, and therefore they are ideal materials to gas sensor. So, we fabricated NOx gas sensors structured MOS-FET using MWCNT (multi-walled carbon nanotubes) material. We investigate the change resistance of NOx gas sensors based on MOS-FET with ultra lean NOx gas concentrations absorption. And NOx gas sensors show sensitivity on the change of gate-source voltage ($V_{gs}=0[V]$ or $V_{gs}=3.5[V]$). The gas sensors show the increase of sensitivity with increasing the temperature (largest value at $40^{\circ}C$). On the other hand, the sensitivity of sensors decreased with increasing of NOx gas concentration. In addition, We obtained the adsorption energy($U_a$), $U_a$ = 0.06714[eV] at the NOx gas concentration of 8[ppm], $U_a$ = 0.06769[eV] at 16[ppm], $U_a$ = 0.06847[eV] at 24[ppm] and $U_a$ = 0.06842[eV] at 32[ppm], of NOx gas molecules concentration on the MWCNT gas sensors surface with using the Arrhenius plots. As a result, the saturation phenomena is occurred by NOx gas injection of concentration for 32[ppm].

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.163-163
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• 1999

MOSFET, MESFET 그리고 MODFET는 Logic ULSIs, high speed ICs, RF MMICs 등에서 중요한 역할을 하고 있으며, 그것의 gate electrode, contact, interconnect 등의 물질로는 refractory metal을 이용한 CoSi2, MoSi2, TaSi2, PtSi2, TiSi2 등의 효과를 얻어내고 있다. 그중 TiSi2는 비저항이 가장 낮고, 열적 안정도가 좋으며 SAG process가 가능하므로 simpler alignment process, higher transconductance, lower source resistance 등의 장점을 동시에 만족시키고 있다. 최근 소자차원이 scale down 됨에 따라 TiSi2의 silicidation 과정에서 C49 TiSi2 phase(high resistivity, thermally unstable phase, larger grain size, base centered orthorhombic structure)의 출현과 그것을 제거하기 위한 노력이 큰 issue로 떠오르고 있다. 여러 연구 결과에 따르면 PAI(Pre-amorphization zimplantation), HTS(High Temperature Sputtering) process, Mo(Molybedenum) implasntation 등이 C49를 bypass시키고 C54 TiSi2 phase(lowest resistivity, thermally stable phase, smaller grain size, face centered orthorhombic structure)로의 transformation temperature를 줄일 수 있는 가장 효과적인 방법으로 제안되고 있지만, 아직 그 문제가 완전히 해결되지 않은 상태이며 C54 nucleation에 대한 physical mechanism을 밝히진 못하고 있다. 본 연구에서는 증착 시 기판온도의 변화(400~75$0^{\circ}C$)에 따라 silicon 위에 DC/RF magnetron sputtering 방식으로 Ti/Si film을 각각 제작하였다. 제작된 시료는 N2 분위기에서 30~120초 동안 500~85$0^{\circ}C$의 온도변화에 따라 RTA법으로 각각 one step annealing 하였다. 또한 Al을 cosputtering함으로써 Al impurity의 존재에 따른 영향을 동시에 고려해 보았다. 제작된 시료의 분석을 위해 phase transformation을 XRD로, microstructure를 TEM으로, surface topography는 SEM으로, surface microroughness는 AFM으로 측정하였으며 sheet resistance는 4-point probe로 측정하였다. 분석된 결과를 보면, 고온에서 제작된 박막에서의 C54 phase transformation temperature가 감소하는 것이 관측되었으며, Al impuritydmlwhswork 낮은온도에서의 C54 TiSi2 형성을 돕는다는 것을 알 수 있었다. 본 연구에서는 결론적으로, 고온에서 증착된 박막으로부터 열적으로 안정된 phase의 낮은 resistivity를 갖는 C54 TiSi2 형성을 보다 낮은 온도에서 one-step RTA를 통해 얻을 수 있다는 결과와 Al impurity가 존재함으로써 얻어지는 thermal budget의 효과, 그리고 그로부터 기대할 수 있는 여러 장점들을 보고하고자 한다.

• Journal of Power Electronics
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• v.16 no.1
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• pp.362-373
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• 2016

The on-line measurement of high-power IGBT collector current is important for the hierarchical control and short-circuit and overcurrent protection of its driver and the sensorless control of the converter. The conventional on-line measurement methods for IGBT collector current are not suitable for engineering measurement due to their large-size, high-cost, low-efficiency sensors, current transformers or dividers, etc. Based on the gate driver, this paper has proposed a current measuring circuit for IGBT collector current. The circuit is used to conduct non-intervention on-line measurement of IGBT collector current by detecting the voltage drop of the IGBT power emitter and the auxiliary emitter terminals. A theoretical analysis verifies the feasibility of this circuit. The circuit adopts an operational amplifier for impedance isolation to prevent the measuring circuit from affecting the dynamic performance of the IGBT. Due to using the scheme for integration first and amplification afterwards, the difficult problem of achieving high accuracy in the transient-state and on-state measurement of the voltage between the terminals of IGBT power emitter and the auxiliary emitter (u_Ee) has been solved. This is impossible for a conventional detector. On this basis, the adoption of a two-stage operational amplifier can better meet the requirements of high bandwidth measurement under the conditions of a small signal with a large gain. Finally, various experiments have been carried out under the conditions of several typical loads (resistance-inductance load, resistance load and inductance load), different IGBT junction temperatures, soft short-circuits and hard short-circuits for the on-line measurement of IGBT collector current. This is aided by the capacitor voltage which is the integration result of the voltage uEe. The results show that the proposed method of measuring IGBT collector current is feasible and effective.

• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.237-241
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• 2000

The structural, electrical and etching characteristics of Al alloy thin film with low impurity concentrations AlNd deposited by using do magnetron sputtering deposition are investigated for the applications as gate bus line in the TFt-LCD panel. And ITO thin film was deposited on AlNd, then the contact resistance was measured by Kelvin resistor. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at $300^{\circ}C$ for 20 min. Moreover, the resistivity of AlNd does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AlNd is found to be hillock free. The etching profiles of AlNd was good and the minimun contact resistance was about $110\;{\mu\Omega}cm$. Calculation results reveal that the AlNd (2wt.%) thin film can be applicable to 25" SXGA class TFT-LCD panels.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.19-23
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• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.118-125
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• 2003

This paper presents a 5.8-㎓ oscillator that uses a novel defected ground structure(DGS), which is etched on the metallic ground plane. As the suggested defected ground structure is the structure for mounting an active device, it is the roles of a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM simulation ,md simple circuit analysis method. In order to demonstrate a new DGS oscillator, we designed the oscillator at 5.8-㎓. The experimental results show 4.17 ㏈m output power with over 22 % dc-to-RF power efficiency and - 85.8 ㏈c/Hz phase noise at 100 KHz offset from the fundamental carrier at 5.81 ㎓.

• Journal of Power Electronics
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• v.15 no.3
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• pp.685-694
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• 2015

The power loss of the controllable switches in modular multilevel converter (MMC) HVDC transmission systems is an important factor, which can determine the design of the operating junction temperatures. Due to the dc current component, the approximate calculation tool provided by the manufacturer of the switches cannot be used for the losses of the switches in the MMC. Based on the enabled probabilities of each SM in an arm, the current analytical models of the switches can be determined. The average and RMS currents can be obtained from the corresponding current analytical model. Then, the conduction losses can be calculated, and the switching losses of the switches can be estimated according to the upper limit of the switching frequency. Finally, the thermal resistance model of the switches can be utilized, and the junction temperatures can be estimated. A comparison between the calculation and PSCAD simulation results shows that the proposed method is effective for estimating the junction temperatures of the switches in the MMC.

• Advances in aircraft and spacecraft science
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• v.4 no.6
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• pp.651-677
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• 2017

For the past ten years' efforts have been made to introduce environmentally-friendly "green" electric-taxi and maneuvering airplane systems. The stated purpose of e-taxi systems is to reduce the taxiing fuel expenses, expedite pushback procedures, reduce gate congestion, reduce ground crew involvement, and reduce noise and air pollution levels at large airports. Airplane-based autonomous traction electric motors receive power from airplane's APU(s) possibly supplemented by onboard batteries. Using additional battery energy storages ads significant inert weight. Systems utilizing nose-gear traction alone are often traction-limited posing serious dispatch problems that could disrupt airport operations. Existing APU capacities are insufficient to deliver power for tractive taxiing while also providing for power off-takes. In order to perform comparative and objective analysis of taxi tractive requirements a "standard" taxiing cycle has been proposed. An analysis of reasonably expected tractive resistances has to account for steepest taxiway and runway slopes, taxiing into strong headwind, minimum required coasting speeds, and minimum acceptable acceleration requirements due to runway incursions issues. A mathematical model of tractive resistances was developed and was tested using six different production airplanes all at the maximum taxi/ramp weights. The model estimates the tractive force, energy, average and peak power requirements. It has been estimated that required maximum net tractive force should be 10% to 15% of the taxi weight for safe and expeditious airport movements. Hence, airplanes can be dispatched to move independently if the operational tractive taxi coefficient is 0.1 or higher.