• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.163-168
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• 2014

Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of $0.1135cm^2/V{\cdot}s$, ${\sim}10^6$, 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at $300^{\circ}C$, $350^{\circ}C$, and $400^{\circ}C$ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1564-1567
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• 2005

Zinc oxide thin films were grown at the t emperature of $100^{\circ}C$ and $150^{\circ}C$ by means of plasma enhanced atomic layer deposition (PEALD) and conventional atomic layer deposition for applying to the transparent thin film transistor (TTFT). The growth rate of $1.9{\AA}/cycle$ with oxygen plasma is similar to that of film grown with water. While the sheet resistivity of ZnO grown with water is 1233 ohm/sq, that of film grown with oxygen plasma was too high to measure with 4 point probe and hall measurement system. The resistivity of the films grown with oxygen plasma estimated to be $10^6$ times larger than that of the films grown with water. The difference of electrical property between two films was caused by the O/Zn atomic ratio. We fabricated ZnO-TFT by means of ALD for the first time and the ZnO channel fabricated with water showed saturation mobility of $0.398cm^2/V{\cdot}s$ with bottom gate configuration.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1572-1575
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• 2005

Poly(vinyl phenol)(PVP)/$TiO_2$ nanocomposite the films have been prepared incorporating metal alkoxide with vinyl polymer to obtain high dielectric constant gate insulating material for a organic thin film transistor. The surface composition, the morphology, and the thermal and electrical properties of the hybrid nanocomposite films were observed by ESCA, scanning electron microscopy (SEM), atomic force microscopy(AFM), and thermogravimetric analysis (TGA). Thin hybrid films exhibit much higher dielectric constants (7.79 at 40wt% metal alkoxide).

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.149-149
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• 2008

Metal-Insulator-Metal(MIM) capacitors have been studied extensively for next generation of high-density dynamic random access memory (DRAM) devices. Of several candidates for metal electrodes, Ru or its conducting oxide $RuO_2$ is the most promising material due to process maturity, feasibility, and reliability. ALD can be used to form the Ru and RuO2 electrode because of its inherent ability to achieve high level of conformality and step coverage. Moreover, it enables precise control of film thickness at atomic dimensions as a result of self-limited surface reactions. Recently, ALD processes for Ru and $RuO_2$, including plasma-enhanced ALD, have been studied for various semiconductor applications, such as gate metal electrodes, Cu interconnections, and capacitor electrodes. We investigated Ru/$RuO_2$ thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru and $RuO_2$ thin films were grown by ALD(Lucida D150, NCD Co.) using RuDi as precursor and O2 gas as a reactant at $200\sim350^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.154-155
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• 2008

대전류용 전력소자를 제조하기 위해 고밀도 트렌치를 형성하여 이들을 병렬로 연결시켜 트렌치 게이트 NMOSFET를 제작하였다. 고밀도 트렌치 소자를 제작한 후 케이트 산화막 두께에 따른 전류-전압 특성을 분석하였다. 트렌치 측벽의 게이트 산화막 두께는 트렌치 측벽의 결정방황에 따라 산화막 두께가 다르게 성장된다. 특히 게이트 산화막 두께의 균일도가 나쁘거나 두꺼울수록 케이트 전류-전압 특성은 다르게 나타난다. 트렌치 형상에 따라 측벽의 산화막 두께가 불균일하거나 혹은 코너 부분의 산화막이 두께가 앓게 증착됨을 알 수 있었다. 이는 트렌치 측벽의 결정방향에 따라 산화막 성장 두께가 다르기 때문이다. 이러한 산화막 두께의 균일도를 향상시키기 위해 트렌치 코너 형상을 개선하여 트렌치 측벽의 게이트 산화막의 두께 균일도를 높였으며, 그 결과 소자의 전기적 특성이 개선되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• 전자공학회논문지 IE
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• v.43 no.2
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• pp.7-10
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• 2006

A GaN-based metal-insulator-semiconductor (MIS) structure has been fabricated by using $BaTa_2O_6$ instead of conventional oxide as insulator gate. The leakage current o) films are in order of $10^{-12}-10^{-13}A/cm^2$ for GaN on $Al_2O_3$(0001) substrate and in order of $10^{-6}-10^{-7}A/cm^2$ for GaN on GaAs(001) substrate. The leakage current of thses films is governed by space-charge-limited current over 45 MV/cm in case of GaN on $Al_2O_3$(0001) substrate and by Poole-Frenkel emission in case of GaN on GaAs(001).