• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.1-7
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• 2012

We have developed a new gate driver circuit for liquid crystal displays using oxide thin-film transistors (TFTs). In the new gate driver, negative gate bias is applied to turn off the oxide TFTs because the oxide TFT occasionally has negative threshold voltage (VT). In addition, we employed three parallel pull-down TFTs that are turned on in turns to enhance the stability. SPICE simulation showed that the proposed circuit worked successfully covering the VT range of -3 V ~ +6 V And fabrication results confirmed stable operation of the new circuit using oxide TFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.276-276
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• 2014

High-performance, fully-transparent, and top-gated oxide thin-film transistor (TFT) was successfully fabricated with Ta2O5 high-k gate dielectric on a glass substrate. Through a self-passivation with the gate dielectric and top electrode, the top-gated oxide TFT was not affected from H2O and O2 causing the electrical instability. Heat-treated InSnO (ITO) was used as the top and source/drain electrode with a low resistance and a transparent property in visible region. A InGaZnO (IGZO) thin-film was used as a active channel with a broad optical bandgap of 3.72 eV and transparent property. In addition, using a X-ray diffraction, amorphous phase of IGZO thin-film was observed until it was heat-treated at 500 oC. The fabricated device was demonstrated that an applied electric field efficiently controlled electron transfer in the IGZO active channel using the Ta2O5 gate dielectric. With the transparent ITO electrodes and IGZO active channel, the fabricated oxide TFT on a glass substrate showed optical transparency and high carrier mobility. These results expected that the top-gated oxide TFT with the high-k gate dielectric accelerates the realization of presence of fully-transparent electronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.196-197
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• 2006

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.6-6
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• 2009

We present an alternative process whereby deuterium is delivered to the location where the gate oxide reside by an implantation process. Deuterium ions were implanted using different energies to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas was performed to remove the D-implantation damage. We have observed that deuterium ion implantation into the gate oxide region can successfully remove the interface states and the bulk defects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• Proceedings of the IEEK Conference
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• summer
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• Korean Journal of Materials Research
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• v.4 no.8
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• pp.921-926
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• 1994

The characteristics of gate oxide significantly depend on the last chemical solution used in cleaning process. The standard RCA, HF-last, SC1-last, and HF-only processes are the pre-gate oxide cleaning processes utilized in this experiment. Cleaning process was followed by thermal oxidation in oxidation furnace at $900^{\circ}C$. A 100$\AA$ gate oxide was grown and characterized with using lifetime detector, VPD AAS, SIMS, TEM, and AFM. The results of HF-last and HF-only were shown to be very effective to remove the metallic impurities. And these two splits also showed long minority carrier lifetimes. The surface and interface morphologies of the oxide were examined with AFM and TEM. The rough surface morphologies were observed with the cleaning splits containing the SC1 solution. The smooth surface and interface was observed with the HF-only cleaning process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.171-175
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• 1996

Gate insulator for Si field emitter is usually formed by e-beam evaporation. However, the evaported oxide requires densification for a stable process and a reduction of gate leakage which results from its Si-rich and nonstoicheiometric structure. In this study, we have developed the process technology able to densify the evaporated oxide in H$_{2}$O ambient. Using this process, we have fabricted thefield emitter array with 625 emitters per pixel, of which gate hole diameter is 1.4.mu.m, for the pixel, anode current of 14.3.mu.A was extracted at a gate bias of 100V and gate leakage was about 0.27% of the total emission current.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.142.1-142.1
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• 2018

This research presents a new field effect transistor (FET) by using liquid crystal gate dielectric with remote gate. The fabrication of thin-film transistors (TFTs) was used Indium tin oxide (ITO) for the source, drain, and gate electrodes, and indium gallium zinc oxide (IGZO) for the active semiconductor layer. 5CB liquid crystal was used for the gate dielectric material, and the remote gate and active layer were covered with the liquid crystal. The output and transfer characteristics of the LC-gated TFTs were investigated.