• 조명전기설비학회논문지
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• 제16권1호
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• pp.13-19
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• 2002

새로운 방전 AND gate를 가지는 플라즈마 디스플레이 패널이 제안되었고 이를 검증하기 위한 구동 회로 시스템이 개발되었다. 그리고 방전 AND gate의 동작이 검증되었다. 방전 AND gate는 8$\mu\textrm{s}$의 동작속도와 20V의 동작마진을 가지고 동작하였으며 인근 주사라인의 방전을 정확히 제어할 수 있다는 것을 알았다. 이 방식은 직류 방전을 사용함으로 종래의 방전 AND gate에 비해 손쉽게 방전을 제어할 수가 있다. 더구나 AND gate의 입력방전과 출력방전이 분리되어 동작하기 때문에 디스플레이 방전이 AND gate를 통과하는 것을 방지할 수 있다. 그러므로 대화면 플라즈마 디스플레이에의 적용이 가능하고 주사방전이 화질에 영향을 주지 않으므로 명암비의 저하가 일어나지 않는다.

• 한국산학기술학회논문지
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• 제21권11호
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• pp.226-232
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• 2020

Stage-Gate 프로세스는 신제품을 아이디어에서 출시로 옮기기 위한 개념 및 운영 모델로, 다양한 신제품 개발 및 연구개발사업에 적용되고 있다. Stage-Gate는 신제품을 시장에 출시하는 것을 목표로 하는 시장 지향적 모델이므로, 대구광역시와 시흥시를 대상으로 실증사업을 진행 중인 스마트시티 혁신성장동력 프로젝트의 운영·관리에 적절히 도입 및 응용 가능하다. 또한 스마트시티는 다양한 혁신 기술 간 융·복합적 특성을 갖는데, Stage-Gate 도입 시, 이를 세분화하여 연구 기관별 성과물 중심의 성과 관리가 가능해진다. 따라서 스마트시티 혁신성장동력 프로젝트(NSSCP: National Strategic Smart City Program)는 국가연구개발사업 최초로 투자 효율성 제고와 연구 성과의 품질 향상, 성공적인 실증 및 사업화를 위하여 Stage-Gate를 적용하였다. 본 논문은 State-Gate 도입 1~2차년도 운영 결과를 검토하고 전문 기관, 연구 기관, 관문심사위원의 의견을 분석하여 향후 차년도 평가체계 운영과 타 연구과제에 적용을 위한 보완 및 개선사항을 제시하였다. Stage-Gate 방법론에 과도하게 몰입되어 경직된 운영에 따른 비효율을 경계하고 해당 사업의 실정에 최적화하여 운영한다면, 스마트시티의 융복합·다학제적 특성에 맞게 성과물 유형에 따른 유연한 평가가 가능할 것으로 기대된다.

• 센서학회지
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• 제30권1호
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

• 전력전자학회논문지
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• 제19권4호
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Ecology and Resilient Infrastructure
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• 제7권4호
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• pp.300-307
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• 2020

본 연구는 다기능 보의 수문 운영 여부에 따라 수생 서식처의 변화를 파악하기 위하여 물리서식처 분석을 수행하였다. 대상 구간은 금강이며, 대상 어종은 피라미를 대상으로 하였다. 흐름 분석은 2차원 모형인 River2D 모형을 사용하였으며, 서식처 분석은 서식처 적합도 곡선을 이용하여 서식처의 양과 질을 산정하는 서식처 적합도 모형을 사용하였다. 수문 개방 여부에 따라 서식처의 변화를 살펴보기 위하여 수문 미개방과 부분개방에 대하여 설정하였다. 그 결과 수문을 부분개방하였을 때 현상태 대비 가중가용면적이 약 13배 향상되는 것으로 나타났다.

• 한국농공학회논문집
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• 제47권6호
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• pp.15-24
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• 2005

The normalization on the characteristics of water level change at the upstream gauging station was attempted according to the operation of drainage sluice gate of the Geumgang estuary dam. The characteristics were normalized by the analysis of water level change and by the linear-regression of the water level data measured at the inner station of Geumgang estuary dam and upstream gauging station. The results of normalization may be referred to the management of Geumgang estuary lake, the operation of pumping and drainage stations in the shore of the lake. The mean response time of water level change on Ibpo, Ganggyeong and Gyuam water level station were 39,81 and 160 minutes, when sluice gate was opened respectively. The mean velocity of surface wave, the mean displacement of water level change, the mean time of water level change and the mean rate of water level change varied largely depending on the location of gauging station and the characteristics of stream section of the water level gauging station.

• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2008년도 학술발표회 논문집
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• pp.26-32
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• 2008

Middle Route Project, the largest water conveyance system in China delivers the water of Changjiang River to North China. In order to create canal operation simulation system, mathematical models are established based on the analysis of hydraulics about steady flow, unsteady flow, and check gate. By simulating the canal operation behavior, we improved the check gate control algorithm and predicted the change process of water surface and flow profile which is very valuable to actual canal operation.

• 한국전기전자재료학회논문지
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• 제21권2호
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.