• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.467-468
• /
• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.207-209
• /
• 2004

Currently, for satisfying the needs of scaled MOSFET's a high quality thin oxide dielectric is desired because the properties of conventional $SiO_2$ film are not acceptable for these very small sized transistors. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over conventional $SiO_2$, to obtain the superior characteristics of ultra thin dielectric films, $N_2O$ grown thin oxynitride has been proposed as a dielectric growtuanneal ambient. In this study the authors observed process characteristics of $N_2O$ grown thin dielectric. In view points of the process characteristics of MOS capacitor, the sheet resistance of 4.07$[\Omega/sq.]$, the film stress of $1.009e^{10}[dyne/cm^2]$, the threshold voltage$(V_t)$ of 0.39[V], the breakdown voltage(BV[V]) of 11.45[V] was measured in PMOS. I could achieve improved electrical characteristics and reliability for deep submicron MOSFET devices with $N_2O$ thin oxide.

• 대한전자공학회논문지SD
• /
• 제38권11호
• /
• pp.765-770
• /
• 2001

고온 급속 열처리시킨 LiNbO₃/AIN/Si(100) 구조를 이용하여 MFIS 소자를 제작하고, 비휘발성 메모리 동작 가능성을 확인하였다. 고유전율 AIN 박막 위에 Pt 전극을 증착시켜 제작한 MIS 구조에서 측정한 1MHz C-V 특성곡선에서는 히스테리시스가 전혀 없고 양호한 계면특성을 보였으며, 축적 영역으로부터 산출한 비유전율 값은 약 8 이었다. Pt/LiNbO₃/AIN/Si(100) 구조에서 측정한 1MHz C-V 특성의 축적영역에서 산출한 LiNbO₃ 박막의 비유전율 값은 약 23 이었으며, ±5 V의 바이어스 범위 내에서의 메모리 윈도우는 약 1.2 V이었다. 이 MFIS 구조에서의 게이트 누설전류밀도는 ±500 kV/cm의 전계 범위 내에서 10/sup -9/ A/㎠ 범위를 유지하였다. 500 kHz의 바이폴러 펄스를 인가하면서 측정한 피로특성은 10/sup 11/ cycle 까지 초기값을 거의 유지하는 우수한 특성을 보였다.

• ETRI Journal
• /
• 제31권6호
• /
• pp.660-666
• /
• 2009

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

• 전기전자학회논문지
• /
• 제26권3호
• /
• pp.500-505
• /
• 2022

본 연구에서는 새로운 구조의 dual gate tri-layer split channel 박막트랜지스터를 제작하였다. 전류 구동 능력을 향상시키기 위해 액티브 층의 양쪽에 게이트를 형성하였고 전하이동도를 증가시키기 위하여 액티브 층에서 채널이 형성되는 구간인 첫번째 층과 세번째 층에 전도성이 높은 ITO 층을 배치하였다. 추가적으로 분할 채널을 이용하여 채널의 series 저항을 낮추면서 분할한 채널의 측면에서도 accumulation을 유도하여 전하이동도를 향상시켰다. 기존의 single gate a-ITGZO 박막트랜지스터가 15 cm²/Vs의 전하이동도를 가지는 반면 dual gate tri-layer split channel 박막트랜지스터는 134 cm²/Vs의 높은 전하이동도를 가졌다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
• /
• pp.661-664
• /
• 2004

In this paper, it was demonstrated that the organic thin film transistors with the organic gate insulators were fabricated by vapor deposition polymerization (VDP) processing. The configuration of OTFTs was a staggered-inverted top-contact structure and gate dielectric layer was deposited with 0.45 ${\mu}m$ thickness. In order to form polyimide as a gate insulator, VDP process was also introduced instead of spin-coating process. Polyimide film was respectively co-deposited with different materials. One was from a 4,4'-oxydiphthalic anhydride (ODPA) and 4, 4'-oxydianiline (ODA) and the other was from 2,2-bis(3,4-dicarboxyphenyl) hexafluoropropane dianhydride (6FDA) and ODA. And it was also cured at 150 $^{\circ}C$ for 1 hour followed by 200 $^{\circ}C$ for 1 hour. Electrical characteristics of the organic thin-film transistors were detailed comparisons between the ODPA-ODA and the 6FDA-ODA which were used as gate insulator.

• Journal of Information Display
• /
• 제11권4호
• /
• pp.165-168
• /
• 2010

A solution-processed multicomponent oxide, yttrium hafnium zinc oxide (YHZO), was synthesized and deposited as a gate insulator. The YHZO film annealed at $600^{\circ}C$ contained an amorphous phase based on the results of thermogravimetry, differential thermal analysis, and X-ray diffraction. The electrical characteristics of the YHZO film were analyzed by measuring the leakage current. The high dielectric constant (16.4) and high breakdown voltage (71.6 V) of the YHZO films resulted from the characteristics of $HfO_2$ and $Y_2O_3$, respectively. To examine if YHZO can be applied to thin-film transistors (TFTs), indium gallium zinc oxide TFTs with a YHZO gate insulator were also fabricated. The desirable characteristics of the YHZO films when used as a gate insulator show that the limitations of the general binary-oxide-based materials and of the conventional vacuum processes can be overcome.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제9권3호
• /
• pp.166-173
• /
• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
• /
• pp.941-943
• /
• 1999

In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.

• E2M - 전기 전자와 첨단 소재
• /
• 제7권5호
• /
• pp.376-382
• /
• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.