• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.165.2-165.2
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• 2011

Flow with suction to water turbine must be in stable state at small hydraulic power plant. But because of water level fluctuation and water gate effect according to irregular supply of cooling water, it would happen to produce bubble and vortex and finally lead to problems in power-plant system. With utilizing the concept design of double size gate, surface water overflowed the overhead of gate for stable flow at suction. We developed the overflow condition and analyzed the design factor with existed one such as water level(overflow amount) and overhead of water gate(overflow figure). Flow test and CFD simulation say that flow have stable state around suction and 20% of wave reduction effect at surface layer after surface water overflow.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• Magazine of the Korean Society of Agricultural Engineers
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• v.45 no.6
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• pp.109-118
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• 2003

As a fundamental research to establish a safety operation plan for irrigation dams, this study presents hydrologic analysis conducted in Sungju Dam watershed based on various rainfall data. Especially those reservoirs without flood control feature are widely exposed to the risk of flooding, a safe and optimized operation program need to be improved against arbitrary flooding. In this study, reservoir routing program was developed and simulated for reservoir runoff estimation using WMS hydrology model. The model simulated the variations of reservoir elevation under the condition of open or closed emergency gate. In case of closed emergency gate, water surface elevation was given as 193.15 m, and this value exceeds the dam crest height by 1.65 m. When the emergency gate is open, the increment of water surface elevation is given as 192.01 m, and this value exceeds dam crest height by 0.57 m. As an alternative plan, dam height increase can be considered for flood control under the PMP (Probable Maximum Precipitation) condition. Since the dam size is relatively small compare to the watershed area, sound protection can be expected from the latter option rather than emergency gate installation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• Proceedings of the IEEK Conference
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• summer
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.263-267
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• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• Journal of Korea Water Resources Association
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• v.51 no.5
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• pp.405-415
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• 2018

Hydraulic variables such as discharge coefficient, gate opening, and upstream water depth are required to calculate the discharge of vertical lift gate. It is very important for a precise gate design, because it may affect the rest, to predict the behavior of gate opening during operation. In this study, an equation by which gate opening could be predicted with any upstream water depths was derived from the relation between the calculated value from buoyancy theory and measured one from experiment for a floating gate model. Downpull force was the reason for the differences between the calculated and the measured and it was verified using pressure coefficient. Also, the relation of discharge coefficient with gate opening ratios was derived. The derived relations were used for flood routing and it was realized that downpull force effect should be fully taken into account during gate design.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.200-204
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• 2012

This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.