• Journal of the Korea Society of Computer and Information
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• v.15 no.10
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• pp.99-104
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• 2010

In this paper, the internal antenna for mobile communication handset which is able to control both coupling coefficient and resonant frequency without any major modification of radiator and ground plane of PIFA(Planner Inverted F Antenna). The resonant frequency as well as amount of coupling between feeding point and shorting post can be adjusted by changing inductance. Because the inductor is connected on shorting post where the strength of electric field is weak, the performance reduction of the proposed antenna is very small enough to neglect. For the variation of the inductance value within 3.3nH, the resonant frequency of antenna can have operating range of 1650MHz ~ 1830MHz. And as be increased the inductance, the coupling coefficient of antenna is over coupled. This means that it can be electrically controlled the resonant frequency and input impedance of antenna by inductance and minimized the mismatch loss. Size reduction of 10% for PIFA is obtained without any major modifications of antenna elements. For the frequency range from 1650 to 1830MHz, reduction of the measured antenna gain is within 0.93dB as varying the value of inductance from 0 to 3.3nH.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.583-591
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• 2008

OFDM (orthogonal frequency division multiplexing) has serious problem of high PAPR (peak-to-average power ratio). Recently, CI/OFDM (carrier interferometry OFDM) system has been proposed for the low PAPR. However, CI/OFDM system shows another problem of ICI because of phase offset mismatch due to the phase noise. In this paper, to simultaneously reduce the PAPR and ICI effects, we propose an A-CI/OFDM (advanced-CT/OFDM). This method improves the BER performance by use of the margin of phase offset at CI codes. Propose system to reduce the effect the phase noise, even though it shows a little bit higher PAPR than conventional CI/OFDM, so we apply the PTS among the PAPR reduction techniques to proposed system to mitigate this problem. Therefore, it improves the total BER performance because the proposed method can decrease the effect of phase noise and get the gain in PAPR reduction performance. From the simulation results, we can show the performance comparison between the conventional OFDM, CI/OFDM and A-CI/OFDM.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.35-40
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• 2013

In this paper, we propose a new image rejection receiver architecture using simultaneously the high-side and low-side injected LO signals. The proposed architecture has a lower noise figure (NF) performance and a higher linearity characteristic than the previous receiver architecture using a single LO signal. Also, the proposed receiver shows a higher IRR performance about 6dB than that of the previous Weaver image rejection architecture even though the same gain and phase errors between I-path and Q-path exist. To verify these characteristics, we derive an IRR formular of the proposed architecture as a function of mismatch parameters. And we demonstrate its formular's usefulness through the system simulation. Therefore, the proposed architecture will be widely used to implement the image rejection receiver due to its higher IRR performance.

• Journal of Information Technology Applications and Management
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• v.26 no.3
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• pp.61-80
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• 2019

The cooperation between universities and industries is already one of the most important factors driving the national economy in the knowledge-based society of the 21st century represented by the Fourth Industrial Revolution. The Korean government has also been carrying out legal and institutional re-adjustments to promote industrial-university cooperation in line with demands for such changes in the times. However, despite this industry-academic cooperation system, there is still a significant mismatch between industrial demand and the university's workforce development system. By the way, there is a Cooperative Education(CO-OP) in Canada and the United States. It's an innovative link between the university and the industry. The reason is that the CO-OP program not only allows students to gain experience with their majors in the industrial field, but also plays a positive role in improving their specialty expertise. In particular, field information, ideas, and job insights that students acquire through CO-OP also serve as motivation for starting a business beyond employment after graduation. Furthermore, CO-OP experience is an important opportunity for future researchers to come up with commercialized research results that are not separated from the field sites The purpose of this study is to overcome the gap between industrial demand and the college manpower training system, and develop a Korean-style coaching program model as a growth engine for creative talent-building policies, represented by 'creation of start-ups and new industry.' In addition, this study suggested measures that can be applied in real universities. In addition, the study also highlighted that the introduction of CO-OP programs with field practices in Korea could also boost start-ups. Based on the Korean CO-OP program model, the curricula applicable to domestic universities consisted of two types : general and research-oriented university types.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.3 s.106
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• pp.239-248
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• 2006

In this paper, the cryogenically cooled low noise amplifier module for radio telescope receiver front-end using pHE-MT MMIC is designed and fabricated. In the selection of MMIC, the MMIC fabricated with the pHEMTS providing successful cryogenic operation are chosen. They are mounted in the housing using the thin film substrate. In the design of the housing, the absorber and the elimination of the gap between the carrier and the housing as well removed the unnecessary oscillations by its structure. The mismatch is improved by ribbon-tuning to provide the best performance at room temperature. The fabricated module shows the gain of $35dB{\pm}1dB$ and the noise figure of $2.37{\sim}2.57dB$ at room temperature over $21.5{\sim}23.5GHz$. In the cryogenic temperature of $15^{\circ}K$ cooled by He gas, the measured gain was above 35 dB and flatness ${\pm}2dB$ and the noise temperatures of $28{\sim}37^{\circ}K$.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.305-305
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• 2014

양자점(Quantum dots)은 3차원적 운반자 구속과 낮은 전류와 높은 온도에서 작동하는 나노 크기의 전기적, 광학적 소자로 응용이 적합하기 때문에 그 특성을 이용한 단전자 트랜지스터, 적외선 검출기, 레이저, LED, 태양전지 등 반도체 소자로의 응용연구가 활발히 진행되고 있다. 특히 양자점의 낮은 임계전류밀도와 높은 차동 이득(differential gain), 그리고 고온에서 작동이 용이하여 양자점 레이저로 활용되고 있다. 이러한 분야에 양자점을 응용하기 위해서는 양자점의 운반자 동역학을 이해하고 양자점의 모양, 크기, 크기 분포와 같은 특성 조절이 필요하다. 또한 기존의 연구들은 III-V족 화합물 반도체 양자점에 대한 연구가 대부분이며, II-VI족으로 구성된 연구가 미흡한 상황이기 때문에 II-VI족 화합물 반도체 양자점에 대한 많은 연구가 필요한 상황이다. II-VI 족 화합물 반도체 양자점은 기존의 III-V 족 양자점보다 더 큰 엑시톤 결합에너지(exciton binding energy)를 가지고 있으며, 이러한 특성을 가지는 II-VI 족 화합물 반도체 양자점 중에서도 CdTe 양자점은 높은 엑시톤 결합에너지와 녹색 스펙트럼 영역을 필요로 하는 광학적 장치들에 응용 가능성이 높기 때문에 더욱 주목받고 있다. 본 연구에서는 분자 선속 에피 성장법(Molecular Beam Epitaxy; MBE)과 원자 층 교대 성장법(Atomic Layer Epitaxy; ALE)으로 CdTe/ZnTe 나노구조에서 ZnTe 완충층의 두께에 따른 운반자 동역학 및 광학적 특성을 연구 하였다. 저온 광루미네센스 측정(Photoluminescence; PL) 을 통하여 ZnTe 완충층 두께가 증가할수록 양자점의 광루미네센스 피크가 낮은 에너지로 이동함을 알 수 있었는데, 이는 ZnTe 완충층의 두께가 증가할수록 ZnTe 완충층과 CdTe 양자점의 격자 불일치(lattice mismatch)로 인한 구조 변형력이 감소하고 이에 따라 CdTe 양자점으로 가해지는 변형(Strain)이 감소하여 CdTe 양자점의 크기가 증가했기 때문이다. 그리고 ZnTe 완충층의 두께가 증가할수록 PL 세기가 증가함을 알 수 있었는데, 이는 ZnTe 완충층의 두께가 증가할수록 양자 구속 효과로부터 electronic state와 conduction band edge 사이의 에너지 차이의 증가 때문이다. 또한 시분해 광루미네센스 측정 결과 ZnTe의 두께가 증가할수록 양자점의 소멸 시간이 더 길게 측정되었는데, 이는 더 큰 양자점 일수록 엑시톤 오실레이터 강도가 감소하기 때문에 더 긴 소멸 시간을 나타내는 것을 확인할 수 있었다. 결과적으로 본 연구는 ZnTe 두께 변화를 통해 양자점의 에너지 밴드를 제어할 수 있으며, 양자점의 효율 향상을 할 수 있는 좋은 방법임을 제시하고 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Information Systems Review
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• v.23 no.3
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• pp.51-75
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• 2021

Global e-commerce websites offer personalized recommendation services to gain sustainable competitiveness. Existing studies have offered personalized recommendation services using quantitative preferences such as ratings. However, offering personalized recommendation services using only quantitative data has raised the problem of decreasing recommendation performance. For example, a user gave a five-star rating but wrote a review that the user was unsatisfied with hotel service and cleanliness. In such cases, has problems where quantitative and qualitative preferences are inconsistent. Recently, a growing number of studies have considered review data simultaneously to improve the limitations of existing personalized recommendation service studies. Therefore, in this study, we identify review and rating mismatches and build a new user profile to offer personalized recommendation services. To this end, we use deep learning algorithms such as CNN, LSTM, CNN + LSTM, which have been widely used in sentiment analysis studies. And extract sentiment features from reviews and compare with quantitative preferences. To evaluate the performance of the proposed methodology in this study, we collect user preference information using real-world hotel data from the world's largest travel platform TripAdvisor. Experiments show that the proposed methodology in this study outperforms the existing other methodologies, using only existing quantitative preferences.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.