• 제목/요약/키워드: fuzzy minimal structures

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Interval- Valued Fuzzy Minimal Structures and Interval-Valued Fuzzy Minimal Spaces

  • Min, Won-Keun
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제8권3호
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    • pp.202-206
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    • 2008
  • We introduce the concept of interval-valued minimal structure which is an extension of the interval-valued fuzzy topology. And we introduce and study the concepts of IVF m-continuous and several types of compactness on the interval-valued fuzzy m-spaces.

FUZZY γ-MINIMAL β-OPEN SETS ON FUZZY MINIMAL SPACES

  • Min, Won-Keun;Kim, Myeong-Hwan
    • 한국수학교육학회지시리즈B:순수및응용수학
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    • 제19권3호
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    • pp.263-271
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    • 2012
  • We introduce the concept of fuzzy $r$-minimal ${\beta}$-open set on a fuzzy minimal space and basic some properties. We also introduce the concept of fuzzy $r-M$ ${\beta}$-continuous mapping which is a generalization of fuzzy $r-M$ continuous mapping and fuzzy $r-M$ semicontinuous mapping, and investigate characterization for the continuity.

Granular Bidirectional and Multidirectional Associative Memories: Towards a Collaborative Buildup of Granular Mappings

  • Pedrycz, Witold
    • Journal of Information Processing Systems
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    • 제13권3호
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    • pp.435-447
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    • 2017
  • Associative and bidirectional associative memories are examples of associative structures studied intensively in the literature. The underlying idea is to realize associative mapping so that the recall processes (one-directional and bidirectional ones) are realized with minimal recall errors. Associative and fuzzy associative memories have been studied in numerous areas yielding efficient applications for image recall and enhancements and fuzzy controllers, which can be regarded as one-directional associative memories. In this study, we revisit and augment the concept of associative memories by offering some new design insights where the corresponding mappings are realized on the basis of a related collection of landmarks (prototypes) over which an associative mapping becomes spanned. In light of the bidirectional character of mappings, we have developed an augmentation of the existing fuzzy clustering (fuzzy c-means, FCM) in the form of a so-called collaborative fuzzy clustering. Here, an interaction in the formation of prototypes is optimized so that the bidirectional recall errors can be minimized. Furthermore, we generalized the mapping into its granular version in which numeric prototypes that are formed through the clustering process are made granular so that the quality of the recall can be quantified. We propose several scenarios in which the allocation of information granularity is aimed at the optimization of the characteristics of recalled results (information granules) that are quantified in terms of coverage and specificity. We also introduce various architectural augmentations of the associative structures.

A novel aerodynamic vibration and fuzzy numerical analysis

  • Timothy Chen;Yahui Meng;Ruei-Yuan Wang;ZY Chen
    • Wind and Structures
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    • 제38권3호
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    • pp.161-170
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    • 2024
  • In recent years, there have been an increasing number of experimental studies showing the need to include robustness criteria in the design process to develop complex active control designs for practical implementation. The paper investigates the crosswind aerodynamic parameters after the blocking phase of a two-dimensional square cross-section structure by measuring the response in wind tunnel tests under light wind flow conditions. To improve the accuracy of the results, the interpolation of the experimental curves in the time domain and the analytical responses were numerically optimized to finalize the results. Due to this combined effect, the three aerodynamic parameters decrease with increasing wind speed and asymptotically affect the upper branch constants. This means that the aerodynamic parameters along the density distribution are minimal. Taylor series are utilized to describe the fuzzy nonlinear plant and derive the stability analysis using polynomial function for analyzing the aerodynamic parameters and numerical simulations. Due to it will yield intricate terms to ensure stability criterion, therefore we aim to avoid kinds issues by proposing a polynomial homogeneous framework and utilizing Euler's functions for homogeneous systems. Finally, we solve the problem of stabilization under the consideration by SOS (sum of squares) and assign its fuzzy controller based on the feasibility of demonstration of a nonlinear system as an example.

Hardware Approach to Fuzzy Inference―ASIC and RISC―

  • Watanabe, Hiroyuki
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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    • pp.975-976
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    • 1993
  • This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

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