• Journal of Broadcast Engineering
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• v.19 no.4
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• pp.521-532
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• 2014

ATSC-M/H based hybrid 3DTV, which is one of the service compatible 3DTV system, has considerable quality gap between the left and right views. And CRA(Conditional Replenishment Algorithm) has been proposed to deal with the issue of resolution mismatch and improve the visual quality. In CRA, the disparity vectors of stereoscopic images are estimated. The disparity compensated left view and simply enlarged right view are compared and conditionally selected for generating the enhanced right view. In order to implement CRA, a fast algorithm is strongly required because the disparity vectors need to be obtained at every layer and the complexity of CRA is quite high. In this paper, we adopted SDSP(Small Diamond Search Pattern) instead of full search and predicted the initial position of search pattern by examining the spatio-temporal correlation of disparity vectors and also suggested the SKIP mode to limit the number of processing units. The computer simulation showed that the proposed fast algorithm could greatly reduce the processing time while minimizing the quality degradation of reconstructed right view.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.56-65
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• 2009

Stereoscopic images consist of the left image and the right image. Thus, stereoscopic images have much amounts of data than single image. Then an efficient image compression technique is needed, the DPCM-based predicted coding compression technique is used in most video coding standards. Motion and disparity estimation are needed to realize the predicted coding compression technique. Their performing algorithm is block matching algorithm used in most video coding standards. Full search algorithm is a base algorithm of block matching algorithm which finds an optimal block to compare the base block with every other block in the search area. This algorithm presents the best efficiency for finding optimal blocks, but it has very large computational loads. In this paper, we have proposed fast disparity estimation algorithm using motion and disparity vector information of the prior frame in stereo image coding. We can realize fast disparity vector estimation in order to reduce search area by taking advantage of global disparity vector and to decrease computational loads by limiting search points using motion vectors and disparity vectors of prior frame. Experimental results show that the proposed algorithm has better performance in the simple image sequence than complex image sequence. We conclude that the fast disparity vector estimation is possible in simple image sequences by reducing computational complexities.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.129-140
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• 1994

In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.156-163
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• 1996

In this paper, we propose VLSI architectures for the full search block matching algorithm (FS BMA) and two-stage BMA using integral projections that reduce greatly computational complexity with its performance comparable to that of the FS BMA. The proposed VLSI architectures are faster than the conventional ones with lower hardware complexity. Also the proposed architectures of the FS BMA and two-stage BMA are modeled in VHDL and simulated to show their functional validity.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.287-290
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• 2002

The block matching algorithm motion estimation is a soft-core for hardwired motion estimation block in MPEG-2, H.261 encoder. This motion estimation has been tested and verified to be valid for implementation of FPGA. Efficiency performance of the synthesized motion estimation was up to 89%, and the average PSNR between the original image and the motion-compensated image is 38dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2762-2770
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• 2012

In this paper, we propose a novel approach to effectively compress the sub-images transformed from the picked-up elemental images in integral imaging, in which motion vectors of the object in each sub-image are fast and accurately estimated and compensated by combined use of MSE(mean square error)-based TSS(tree-step search) and FS(full search) schemes. This is, the possible object areas in each sub-image are searched by using the fast TSS algorithm in advance, then the these selected object areas are fully searched with the accurate FS algorithm. Furthermore, the sub-images in which all object's motion vectors are compensated, are transformed into the residual images by using the difference image method and finally compressed with the MPEG-4 algorithm. Experimental results reveal that the proposed method shows 214% improvement in the compression time per each image frame compared to that of the conventional method while keeping the same compression ratio with the conventional method. These successful results confirm the feasibility of the proposed method in the practical application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.836-839
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• 2016

In this paper, we propose a motion estimation method that is important in performance of video encoding. Conventional motion estimation methods have serious problems of low prediction quality and problems of much computation increase. In the paper, we propose a method that reduces unnecessary computations only using optimal candidate points, while keeping prediction quality almost similar to that of the full search. The proposed method takes only 3~5% in computational amount and has decreased prediction quality about 0~0.01dB compared with the fast full search algorithm.

• Structural Engineering and Mechanics
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• v.54 no.2
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• pp.305-317
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• 2015

Optimal sensor placement (OSP) is an integral component in the design of an effective structural health monitoring (SHM) system. This paper describes the implementation of a novel collaborative-climb monkey algorithm (CMA), which combines the artificial fish swarm algorithm (AFSA) with the monkey algorithm (MA), as a strategy for the optimal placement of a predefined number of sensors. Different from the original MA, the dual-structure coding method is adopted for the representation of design variables. The collaborative-climb process that can make the full use of the monkeys' experiences to guide the movement is proposed and incorporated in the CMA to speed up the search efficiency of the algorithm. The effectiveness of the proposed algorithm is demonstrated by a numerical example with a high-rise structure. The results show that the proposed CMA algorithm can provide a robust design for sensor networks, which exhibits superior convergence characteristics when compared to the original MA using the dual-structure coding method.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.823-824
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• 2008

In this paper, we propose a robust and fast digital image stabilization algorithm based on edge detection. The proposed algorithm exploits sobel operator to obtain edge image and fast detects irregular conditions with analyzing an edge information of the image. Experimental results show that the proposed algorithm can gain better performance in the sense of speed and precision comparing with full-block search method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.