Hardware Design of a Two-Stage Fast blck Matching Algorithm Using Integral Projections

거상투영을 이용한 2단계 고속 블록정합 알고리즘의 하드웨어 설계

In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.