• 전력전자학회논문지
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• 제25권1호
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• pp.21-28
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• 2020

Integrated bidirectional OBC/LDC was developed to reduce the volume for elements, avoid space restriction, and increase efficiency in EV vehicles. In this study, a DC-DC converter in integrated OBC/LDC circuits was composed of an SRC circuit with a stable output voltage relative to an LLC circuit using a theoretical method and simulation. The resonant network of the selected circuit was optimized to minimize the power loss and element volume under constraints for the buck converter and the battery charging range. Moreover, the validity of the optimal model was verified through an analysis using a theoretical method and a numerical analysis based on power loss at the optimized resonant frequency.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.1196-1198
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• 2002

A novel single-stage half-bridge high frequency resonant inverter using ZVS(Zero Voltage Switching) with high input power factor suitable for induction heating applications is presented in this paper. The proposed high frequency resonant inverter integrates half-bridge boost rectifier as power factor corrector(PFC) and half-bridge resonant inverter into a single stage. The input stage of the half-bridge boost rectifier is working in discontinuous conduction mode (DCM) with constant duty cycle and variable switching frequency. So that a high power factor is achieved naturally. Simulation results through the Pspice have demonstrated the feasibility of the proposed inverter. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of Power Electronics
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• 제18권6호
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• pp.1791-1804
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• 2018

To achieve a fast dynamic response and to solve the multi-objective control problems of the output currents, capacitor voltages and system constraints, this paper proposes a deadbeat and hierarchical predictive control with space-vector modulation (DB-HPC-SVM) for five-level nested neutral point piloted (NNPP) converters. First, deadbeat control (DBC) is adopted to track the reference currents by calculating the deadbeat reference voltage vector (DB-RVV). After that, all of the candidate switching sequences that synthesize the DB-RVV are obtained by using the fast SVM principle. Furthermore, according to the redundancies of the switch combination and switching sequence, a hierarchical model predictive control (MPC) is presented to select the optimal switch combination (OSC) and optimal switching sequence (OSS). The proposed DB-HPC-SVM maintains the advantages of DBC and SVM, such as fast dynamic response, zero steady-state error and fixed switching frequency, and combines the characteristics of MPC, such as multi-objective control and simple inclusion of constraints. Finally, comparative simulation and experimental results of a five-level NNPP converter verify the correctness of the proposed DB-HPC-SVM.

• Journal of Power Electronics
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• 제16권5호
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• pp.1884-1893
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• 2016

The ride-through control of a doubly-fed induction generator (DFIG) for the voltage sags on wind farms utilizing crowbar circuits by which the rotor side converter (RSC) is disabled has being reported in many literatures. An analysis and calculation of the transient current when the RSC is switched off are of significance for carrying out the low voltage ride through (LVRT) of a DFIG. The mathematical derivation is highlighted in this paper. The zero-state and zero-input responses of the transient current in the frequency domain through a Laplace transformation are investigated, and the transient components in the time domain are achieved. With the characteristics worked out from the linear resolving without modeling simplification, the selection of the resistance in the linear crowbar circuit and the value conversion from a linear circuit to a nonlinear one is proposed to setup the attenuation rate. In terms of grid code requirements, the theoretical analysis for the time constant of the transient components attenuation insures the controllability when the excitation of the RSC is resumed and it guarantees the reserved time for the response of the reactive power compensation. Simulations are executed in MATLAB/SIMPOWER and experiments are carried out to validate the theoretical analysis. They indicate that the calculation method is effective for selection of the resistance in a crowbar circuit for LVRT operations.

• 한국철도학회논문집
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• 제20권3호
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• pp.329-338
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• 2017

최근 철도차량용 보조전원장치는 시스템의 경량화를 위해 기존 60Hz 저주파 변압기를 제거하고 고주파 구동과 절연 특성을 갖는 '절연형 dc/dc 컨버터'를 적용하는 구조가 주목받고 있다. 본 논문에서는 '절연형 dc/dc 컨버터를 적용한 보조전원장치 구조'에 대해서 설명하고, 다양한 분석을 통해 보조전원장치의 고효율 및 경량화에 적합한 dc/dc 컨버터 및 구조를 제안하고자 한다. 대용량 IGBT 소자의 고주파 스위칭(경량화)을 위해 필수적인 '영전압-영전류-스위칭'특성을 갖는 '공진형 컨버터'를 활용하여 다양한 보조전원장치용 전력변환장치 구조(1-Stage와 2-Stage)를 제안하였고, 각각의 구조에 적합한 컨버터 회로를 선정한 후 설계 및 시뮬레이션을 통해 비교하였다. 1-Stage 구조의 경우 공진형 컨버터만을 사용하였고, 2-Stage 구조의 경우 공진형 컨버터와 공진형 컨버터의 입력전압 변동을 최소화하는 Pre-regulator를 적용하였다. Pre-regulator로서 감압 컨버터 또는 승압 컨버터를 각각 적용하여 서로 다른 2-Stage 구조를 구성하고 각 방식의 손실을 비교하였다. 회로에 사용되는 소자들의 전압 및 전류 스트레스를 고려하여 소자를 선정하고 시뮬레이션을 통해 동작을 검증하였으며, 손실 분석을 통해 고효율 및 경량화에 가장 적합한 구조 및 회로를 제안하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.108-113
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• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

• Journal of Power Electronics
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• 제12권5호
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• pp.787-799
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• 2012

Real and reactive power flows on a transmission line interact inherently. This situation degrades power flow controller performance when independent real and reactive power flow regulation is required. In this study, a quasi multi-pulse interline power flow controller (IPFC), consisting of eight six-pulse voltage source converters (VSC) switched at the fundamental frequency is proposed to control real and reactive power flows dynamically on a transmission line in response to a sequence of set-point changes formed by unit-step reference values. It is shown that the proposed hybrid fuzzy-PI commanded IPFC shows better decoupling performance than the parameter optimized PI controllers with analytically calculated feed-forward gains for decoupling. Comparative simulation studies are carried out on a 4-machine 4-bus test power system through a number of case studies. While only the fuzzy inference of the proposed control scheme has been modeled in MATLAB, the power system, converter power circuit, control and calculation blocks have been simulated in PSCAD/EMTDC by interfacing these two packages on-line.

• 대한전자공학회논문지SD
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• 제47권2호
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• pp.60-67
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• 2010

본 논문에서는 입력 전류를 정현파가 되도록 제어하기 위하여 boost 인덕터 전류의 평균값이 정현파 모양을 따라가도록 하는 평균전류 제어 방식의 PFC IC를 설계하였다. 설계된 IC는 EMI 규격에 적합하도록 75kHz의 고정주파수를 가지고 고속 제어를 위해 넓은 대역폭을 갖도록 오차 증폭기 및 전류 증폭기에 RC 보상 루프를 구성하였다. 또한 시스템 내부의 오실레이터를 이용해 구형파와 삼각파를 발생시켜 역률제어에 적합한 신호를 생성하고, UVLO, OVP, OCP, TSD의 회로를 추가하여 시스템이 안정적으로 동작이 되도록 하였다. 설계된 IC는 $1{\mu}m$ High Voltage(20V) CMOS 공정을 이용하였고, 역률보정기능과 각종 보호 회로를 검증하기 위해 Cadence의 Spectre simulator를 이용하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.665-667
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• 2010

본 논문에서는 주파수 하향 변환기를 이용한 전력증폭기의 혼변조 성분 검출 방법을 제안하였다. 전력증폭기 출력 신호의 일부를 전력분배기를 통해 2개의 경로로 나누어 변환기의 RF, LO 단자에 각각 인가한 뒤 그 차 주파수를 얻고, 얻어진 차 주파수 중 필요한 성분인 3차와 5차의 차 성분만 여파기로 걸러 내어 이를 DC 전압으로 변환함으로써 전력 증폭기 출력 신호의 혼변조 성분의 크기를 알 수 있었다. 3W 전력증폭기의 Vgs를 변화시켜서 3차 혼변조 성분이 -26.4~+2.15dBm, 5차 혼변조 성분이 -34.2~-12.89dBm으로 변화하였을 때, 검출된 DC 전압 크기는 +0.72~+0.9V의 변화를 보였다.