1 |
B. P. Ginsburg and A. P. Chandrakasan, "An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC," in Proc. IEEE Int. Sym. Circuits and System, 2005, vol. 1, pp. 184-187.
|
2 |
Michael D. Scott, Bernhard E. Boser and Kristofer S. J. Pister, "An Ultralow-Energy ADC for Smart Dust," IEEE J. Solid-state Circuits, vol. 38, pp. 1123-1129, July 2003.
DOI
ScienceOn
|
3 |
Pieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, and Harmke de Groot, "A 30fJ/Conversion-Step 8b 0-to-10 MS/s Asynchronous SAR ADC in 90nm CMOS", ISSCC Dig. Tech Papers, pp.387-389, Feb. 2010
|
4 |
Peng Zhu Yan, Chi-Hang Chan, Maloberti F., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-state circuits, pp.1111-1121, June., 2010
|
5 |
Sin Sai-Weng, Ding Li, Zhu Yan, Maloberti Franco, "An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H", ESSCIRC, pp.218- 221, Sept., 2010
|
6 |
Hao-Chiao Hong and Guo-Ming Lee, "A 65- fJ/Conversion-Step 0.9-V 200kS/s Rail-to-Rail 8-bit Successive Approximation ADC", IEEE Journal of Solid-state circuits, Vol. 42, no.10, Oct. 2007.
|
7 |
M. Miyahara, M. Asada, D. Paik and A. Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADC," Proc. of ASSCC, pp. 269-272, Nov. 3-5, 2008
|