• Publications of The Korean Astronomical Society
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• v.20 no.1 s.24
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• pp.73-83
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• 2005

On-The-Fly (OTF) observation method is developed for the efficient use of 6 M radio telescope at Seoul Radio Astronomy Observatory (SRAO). This technique, in which data and information of antenna position are recorded synchronously while driving a telescope regularly and rapidly across a field, provides more efficient use of telescope time and better calibration of the acquired data than the traditional point-to-point observation method does. For the realization of the method, we (1) added RT-Linux modules to the existing operating system, (2) replaced digital voltmeter with voltage-to-frequency converter, and (3) modified many SRAO observation programs. By observing Moon and G78.2+2.7 using this method and comparing them with previous observations, we verify the successful operation and efficiency of the OTF observation mode.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2000.10a
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• pp.222-227
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• 2000

"Side scan sonar" using acoustic signal has been developed to survey cable laying, sunken bodie\ulcorner bottom and so on. It use the acoustic signals, which are emitted from two transducer arrays, to get gemetri\ulcorner target area. This system consists of transceiver board, towed body, and deck unit. The transceiver board, w\ulcorner watertight canister of the towed body, controls the transmitting and receiving of 400kHz acoustic signals from \ulcorner After receiving the scattered signals, it processes the filtering, AGF(Automatic Gain Control), TVG(Time Heterodyne. The deck unit is composed of the signal processing part, A/D converter, power supplier, and real\ulcorner And the towed body has been designed to satisfy the optimal hydrodynamic behavior during towing. The de\ulcorner theory of transceiving part and some results from field-experiments will be introduced here.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.1
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• pp.51-58
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• 2001

Recently, DC-DC converters significantly increase the total losses as rising switching frequency. Trnditional soft switching technique for reducing switching losses even increase voltage/Clment stress of switch In this paper, Resonant circuit for soft switching is connected in parallel with power stage and only operates just before tum-on of the main sWItch. Therefore, ills doesn't affect the total circuit QI'||'&'||'pound;ration. The object of tIns paper is to make the linearized equivalent loss mxleIs. and to analyze the total losses by experiment. ZVT-PWlvI converter designed with 170-260[V] input, 400[V] 5[A] output, and 100[kHz] switching frequency is tested respectively with 500[W], 1[kW], 1.5[kW], and 2[kW] loads. The total losses in input 220[V], 2[kW] load are analyzed by usirm the linearized equivalent loss models.

• Journal of Power Electronics
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• v.13 no.6
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• pp.1058-1069
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• 2013

This paper proposes and designs a new output filter called an LCFL filter for application to three phase three wire shunt active power filters (SAPF). This LCFL filter is derived from a traditional LCL filter by replacing its capacitor with a C-type filter, and then constructing an L-C-type Filter-L (LCFL) topology. The LCFL filter can provide better switching ripple attenuation capability than traditional passive damped LCL filters. The LC branch series resonant frequency of the LCFL filter is set at the switching frequency, which can bypass most of the switching harmonic current generated by a SAPF converter. As a result, the power losses in the damping resistor of the LCFL filter can be reduced when compared to traditional passive damped LCL filters. The principle and parameter design of the LCFL filter are presented in this paper, as well as a comparison to traditional passive damped LCL filters. Simulation and experimental results are presented to validate the theoretical analyses and effectiveness of the LCFL filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.45-52
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• 2008

We investigated the design of an RF-powered, wireless temperature sensor tag chip using $0.18-{\mu}m$ CMOS technology. The transponder generates its own power supply from small incident RF signal using Schottky diodes in voltage multiplier. Ambient temperature is measured using a new low-power temperature-to-voltage converter, and an 8-bit single-slope ADC converts the measured voltage to digital data. ASK demodulator and digital control are combined to identify unique transponder (ID) sent by base station for multi-transponder applications. The measurement of the temperature sensor tag chip showed a resolution of $0.64^{\circ}C/LSB$ in the range from $20^{\circ}C$ to $100^{\circ}C$, which is suitable for environmental temperature monitoring. The chip size is $1.1{\times}0.34mm^2$, and operates at clock frequency of 100 kHz while consuming $64{\mu}W$ power. The temperature sensor required a -11 dBm RF input power, supported a conversion rate of 12.5 k-samples/sec, and a maximum error of $0.5^{\circ}C$.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• ETRI Journal
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• v.21 no.3
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• pp.1-5
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• 1999

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.516-520
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• 1991

This paper presents a comparative analysis of two inverter power supply topologies for induction heating and melting applications. The comparison is based on criteria such as resonant condition, component ratings, minimum and maximum operating frequencies, operation under varying load conditions, inverter starting current, and diode reverse recovery time. The voltage source series/parallel resonant inverters are found to offer the best overall performance with respect to converter utilization.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.6
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• pp.441-449
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• 2000

Analysis, design and practical implementation of a single-stage electronic ballast for compact fluorecent lamps are presented in this paper. The proposed topology is based on a single-stage ballast which combines a boost converter and a half-bridge series resonant inverter. High power factor is achieved by using the boost semi-stage operating in discontinuous conduction mode, and inverter semi-stage operated above resonant frequency to provide zero voltage switching is employed to ballast the fluorescent lamp. Analytical and experimental results from the ballast system with 36W fluorescent lamps have demonstrated the feasibility of the proposed single-stage electronic ballast.