• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.1
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• pp.21-28
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• 2020

Integrated bidirectional OBC/LDC was developed to reduce the volume for elements, avoid space restriction, and increase efficiency in EV vehicles. In this study, a DC-DC converter in integrated OBC/LDC circuits was composed of an SRC circuit with a stable output voltage relative to an LLC circuit using a theoretical method and simulation. The resonant network of the selected circuit was optimized to minimize the power loss and element volume under constraints for the buck converter and the battery charging range. Moreover, the validity of the optimal model was verified through an analysis using a theoretical method and a numerical analysis based on power loss at the optimized resonant frequency.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1196-1198
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• 2002

A novel single-stage half-bridge high frequency resonant inverter using ZVS(Zero Voltage Switching) with high input power factor suitable for induction heating applications is presented in this paper. The proposed high frequency resonant inverter integrates half-bridge boost rectifier as power factor corrector(PFC) and half-bridge resonant inverter into a single stage. The input stage of the half-bridge boost rectifier is working in discontinuous conduction mode (DCM) with constant duty cycle and variable switching frequency. So that a high power factor is achieved naturally. Simulation results through the Pspice have demonstrated the feasibility of the proposed inverter. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1791-1804
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• 2018

To achieve a fast dynamic response and to solve the multi-objective control problems of the output currents, capacitor voltages and system constraints, this paper proposes a deadbeat and hierarchical predictive control with space-vector modulation (DB-HPC-SVM) for five-level nested neutral point piloted (NNPP) converters. First, deadbeat control (DBC) is adopted to track the reference currents by calculating the deadbeat reference voltage vector (DB-RVV). After that, all of the candidate switching sequences that synthesize the DB-RVV are obtained by using the fast SVM principle. Furthermore, according to the redundancies of the switch combination and switching sequence, a hierarchical model predictive control (MPC) is presented to select the optimal switch combination (OSC) and optimal switching sequence (OSS). The proposed DB-HPC-SVM maintains the advantages of DBC and SVM, such as fast dynamic response, zero steady-state error and fixed switching frequency, and combines the characteristics of MPC, such as multi-objective control and simple inclusion of constraints. Finally, comparative simulation and experimental results of a five-level NNPP converter verify the correctness of the proposed DB-HPC-SVM.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1884-1893
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• 2016

The ride-through control of a doubly-fed induction generator (DFIG) for the voltage sags on wind farms utilizing crowbar circuits by which the rotor side converter (RSC) is disabled has being reported in many literatures. An analysis and calculation of the transient current when the RSC is switched off are of significance for carrying out the low voltage ride through (LVRT) of a DFIG. The mathematical derivation is highlighted in this paper. The zero-state and zero-input responses of the transient current in the frequency domain through a Laplace transformation are investigated, and the transient components in the time domain are achieved. With the characteristics worked out from the linear resolving without modeling simplification, the selection of the resistance in the linear crowbar circuit and the value conversion from a linear circuit to a nonlinear one is proposed to setup the attenuation rate. In terms of grid code requirements, the theoretical analysis for the time constant of the transient components attenuation insures the controllability when the excitation of the RSC is resumed and it guarantees the reserved time for the response of the reactive power compensation. Simulations are executed in MATLAB/SIMPOWER and experiments are carried out to validate the theoretical analysis. They indicate that the calculation method is effective for selection of the resistance in a crowbar circuit for LVRT operations.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.329-338
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• 2017

A recent trend of technical development in auxiliary-power-supplies (APS) is to replace 60Hz low frequency transformers with isolated type dc/dc converters. This paper introduces the technical trend in APS structures and proposes a power converter circuit suitable for high-efficient and light-weight APS. By utilizing the resonant converter, which achieves ZCS, to reduce switching losses, various types of APS structures (1-stage and 2-stage) are reviewed, and they are verified by simulation. The full-bridge resonant LLC converter is designed with a 1-stage power converting structure; the resonant converter topology is designed with a 2-stage power converting structure that has a pre-regulator converter to compensate for the wide input voltage range. Both a step-down converter and a step-up converter are designed and compared for the pre-regulator in the 2-stage structure. Operational characteristics are compared with simulation results and loss analyses are presented to proposes appropriate system structure and topologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.108-113
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• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

• Journal of Power Electronics
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• v.12 no.5
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• pp.787-799
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• 2012

Real and reactive power flows on a transmission line interact inherently. This situation degrades power flow controller performance when independent real and reactive power flow regulation is required. In this study, a quasi multi-pulse interline power flow controller (IPFC), consisting of eight six-pulse voltage source converters (VSC) switched at the fundamental frequency is proposed to control real and reactive power flows dynamically on a transmission line in response to a sequence of set-point changes formed by unit-step reference values. It is shown that the proposed hybrid fuzzy-PI commanded IPFC shows better decoupling performance than the parameter optimized PI controllers with analytically calculated feed-forward gains for decoupling. Comparative simulation studies are carried out on a 4-machine 4-bus test power system through a number of case studies. While only the fuzzy inference of the proposed control scheme has been modeled in MATLAB, the power system, converter power circuit, control and calculation blocks have been simulated in PSCAD/EMTDC by interfacing these two packages on-line.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.60-67
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• 2010

We designed Average Current Control PFC IC which has make the average value of boost inductor current became the shape of sine wave. Designed IC has fixed frequency of 75kHz to meet EMI standard requirement. And also RC compensation loop has been designed into the error amp and the current amp, in order that it has wide bandwidth for high speed control. And we use the oscillator which generates by square wave and triangle wave, and add to UVLO, OVP, OCP, TSD which is in order to operate stability. We simulated by using Spectre of Cadence to verify the unity power factor function and various protection circuits and fabricated in a $1{\mu}m$ High Voltage(20V) CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.665-667
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• 2010

In this paper, the method to detect the IM(Inter Modulation) components of power amplifier is proposed by using frequency down-convertor. Output signals of power amplifier which is coupled by 20dB coupler and divided by power divider are applied to RF and LO of the frequency converter. It could be found the magnitude of IM components of power amplifier as a converted DC voltage which is come from the difference between 3th and 5th IM component. The detected DC voltage values are changed from 0.72V to 0.9V when 3rd IM component level changed from -26.4dBm to +2.15dBm and 5th IM component level changed from -34.2dBm to -12.89dBm as the Vgs of 3W power amplifier is changed.