• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.131-142
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• 2005

The low rate speech coders under 4 kbit/s are based on sinusoidal transform coding (STC) or multiband excitation (MBE). Since the harmonic coders are not efficient to reconstruct the transient segments of speech signals such as onsets, offsets, non-periodic signals, etc, the coders do not provide a natural speech quality. This paper proposes method of a efficient transient model :d a multi-mode low rate coder at 2.4 kbit/s that uses harmonic model for the voiced speech, stochastic model for the unvoiced speech and a model using aperiodic pulse location tracking (APPT) for the transient segments, respectively. The APPT utilizes the harmonic model. The proposed method uses different models depending on the characteristics of LPC residual signals. In addition, it can combine synthesized excitation in CELP coding at time domain with that in harmonic coding at frequency domain efficiently. The proposed coder shows a better speech quality than 2.4 kbit/s version of the mixed excitation linear prediction (MELP) coder that is a U.S. Federal Standard for speech coder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1096-1103
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• 2008

This paper proposes an individual order predistortion linearizer using intermodulation distortion(IMD) generator for cancellation the third and the fifth IMD of power amplifier. The IMD generator for controlling the third and the fifth IMD consist of common Emitter amplifier and Schottky diode. These signals are generated by series feedback of Schottky diode to obtain the inverse AM/AM and AM/PM characteristics of power amplifier. The individual order predistorters are consisted of individual IMD generator, power splitter and combiner. The test results show that the third and the fifth IMD can be improved by a maximum 13.5 dB and 0.9 dB in case of CW 2-tone signals. Also, the Adjacent Channel Leakage Ratio(ACLR) can be improved 2.3 dB, 2.5 dB at ${\pm}0.885$ MHz, ${\pm}1.23$ MHz offset frequency for CD-MA IS-95 2FA signals.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.53-59
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• 2008

In this paper, a novel dual-band high-efficiency class-F power amplifier using the composite right/left-handed (CRLH) transmission lines (TLs) has been realized with one RF Si lateral diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET). The CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of the all harmonic components is very difficult in dual-band, we have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency. Two operating frequencies are chosen at 880 MHz and 1920 MHz in this work. The measured results show that the output power of 39.83 dBm and 35.17 dBm was obtained at 880 MHz and 1920 MHz, respectively. At this point, we have obtained the power-added efficiency (PAE) of 79.536 % and 44.04 % at two operation frequencies, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1040-1049
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• 2006

A design method for minimizing transmission loss of a broadband right-angle transition from a coaxial cable to a microstrip line is presented. The right-angle transition has been widely used where printed circuit applications need to be fed from behind the ground plane using coaxial line. To obtain the minimized transmission loss over the whole operating frequency range of the transition, design parameters such as ground aperture and probe diameters, ground aperture offset, and stub length are optimized using a commercial electromagnetic simulation software. Results are presented for the optimum right-angle transition from an SMA connector to a microstrip line on common reinforced 0.787 mm thick PTFE substrates. Measurements of a fabricated transition show that reflection coefficient is less than -22 dB and insertion loss is less than 0.45 dB over $0.05{\sim}20GHz$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• Analyses & Alternatives
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• v.6 no.2
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• pp.117-154
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• 2022

The purpose of this study is to verify the practical validity of financial sanctions, which has recently emerged as the most powerful form of economic sanctions preferred by U.S. foreign policy tool. Based on the theoretical discussion, analyse this study the trend of de-dollarization appearing in connection with financial sanctions and argue that the effectiveness of financial sanctions erode the dollar financial hegemony, which is the source of its power can be degraded, so that its effectiveness could not be so great as most people likely think about. After World War II, there has been an increasing tendency in the international community to favor economic sanctions over the use of military force as an effective means of foreign policy. Among these economic sanctions, a distinct feature that has recently appeared is the remarkable increase in the frequency of use of financial sanctions. The country that favors financial sanctions most is the United States. The reason is that they believe that the power of their own dollar financial hegemony can exert deadly pressure on other countries. Financial sanctions favored by the United States are said to have increased the effectiveness of sanctions by upgrading the pressure of sanctions to the next level. Nevertheless, financial sanctions have a side that underestimates the cost. This problem is found in the signs that the backlash from not only countries subject to financial sanctions but also many countries with interests in these countries is leading to a tendency to de-dollarization. This study will try to see how likely this de-dollarization trend is to offset the effectiveness of financial sanctions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.