• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.5
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• pp.516-522
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• 2020

In this paper, the frequency detector which detects the clock frequency of the embedded system is proposed and analyzed. The proposed frequency detector is consisted of filter and peak voltage detector. The clock signal is converted from square wave to triangular wave by the filter. The peak voltage of the triangular wave is determined according to the frequency response of filter. The peak voltage detector detects and holds the peak voltage of the signal. Moreover, the proposed clock frequency detector can detect the frequency within 1ms and it gives guarantee of real-time operation.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.718-720
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• 1999

This paper describes a charge pump PLL architecture which achieves high frequency operation and fast acquisition. This architecture employs multi-phase frequency detector comprised of precharge type phase frequency detector and conventional phase frequency detector. Operation frequency is increased by using precharge type phase frequency detector when the phase difference is small and acquisition time is shortened by using conventional phase frequency detector and increased charge pump current when the phase difference is large. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 694MHz at 3.0V and faster acquisition were achieved by simulation.

• Journal of Advanced Marine Engineering and Technology
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• v.23 no.2
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• pp.210-215
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• 1999

The proposed detector is consists of three-phase sinusoidal signal generator and peak detector. This peak detector can detect the peak voltage value at the state of variable frequency. In experi-ment three-phase sinusoidal signals are generated from D/A converter using IBM PC and deliv-ered to the peak detector. Each signals are squared by multiplier and summed up Peak value is the square root of summed value extracted by square root circuit.

• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.685-692
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• 2008

In this paper, we propose a timing recovery loop for Inmarsat mini-m system downlink receiver. Inmarsat mini-m system requires a timing recovery loop which is robust in frequency offset and has fast acquisition because Inmarsat mini-m system specification requires frequency tolerance is required of ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) and acquisition time of UW (Unique Word) signal duration (15ms).Therefore, we propose a timing recovery loop which is suitable for Inmarsat mini-m system. The proposed timing recovery loop adopted noncoherent UW detector and differential ELD which applied differential UW signal for stability and fast acquisition in frequency offset environment. Simulation results show that the proposed timing recovery loop has stable operation and fast acquisition in frequency offset environment for the system.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.609-611
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• 1996

Zero-Cross Detector makes pilot signal to control the power to CEDM(Control Element Drive Mechanism). Existing Zero-Cross Detectors has had a problem which can cause unexpected reactor trip resulted from fluctuating frequency of input signal coming from M/G Set. The existing Zero-Cross Detector can't work properly when power frequency is varying because it was designed to work under stable M/G Set operation, and produces wrong pilot signal and output voltage. In this report the Zero-Cross Detector is improved to resolve voltage fluctuating problem by using new devices such as digital noise filtering circuit, variable cycle compensator and alarm circuit. And through the performance verification it shows that new circuit is better than old one. If suggested detector is applied to plant, it is possible to use it under House Load Operation because stable voltage can be generated by new Zero-Cross Detector.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.615-618
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• 2006

The broadband power detector for direct- onversion Six-port output circuit was designed and implementaed in this paper. The power detector should linearly operated to produce the linear amplitude and phase signal fer input RF signal in required broadband. So, the power detector should be designed under conditions of matching circuit with low VSWR. The designed power detectors, which were implemented in L-band with 50 ohm matching and Ku-band with matching circuit and isolator, respectively, were evaluated in the performances.

• Journal of Sensor Science and Technology
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• v.13 no.2
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• pp.133-138
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• 2004

Today, the obstacle detection system has massive size and restrictive detection range. To solve these problems, this paper proposes the capacitance variation detector using the variated capacitance value as a result of the obstacle approaching. If obstacle approaches, the capacitance value of capacitance sensor is increased and the operating frequency of oscillator is decreased. Then this changed frequency appears to the output of the mixer that operate down conversion. The capacitance variation detector is produced by Hynix$0.35{\mu}$ CMOS process. In experiment result, the frequency of final output is 6.81 MHz at no obstacle and 31.45 MHz at approaching obstacle. In conclusion, proposed capacitance variation detector has small size, low power consumption and easiness to set up anywhere. So it is expected to substitute the obstacle detector.