• 전자공학회논문지C
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• 제34C권10호
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2001년도 봄 학술발표논문집 Vol.28 No.1 (A)
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• pp.187-189
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• 2001

In this study, the Web Camera System is implementation and simulated on two different architectures. In the one architecture, a Web-server and Camera-server are implemented on the same system, and the system transfers motion picture which compressed to JPEG file to users on the WWW(World Wide Web). In the other architecture, the Web-server and Camera-server are implemented on different systems, and the motion picture is transferred from the Camera-server to Web-server, and finally to users. In order to compare system performance between two architecture, data traffic is measured and simulated in the unit of byte per second and frame per second.

• 한국방사선학회논문지
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• 제12권7호
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• pp.845-852
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• 2018

본 연구는 심장 혈관 조영술의 투시 영상과 씨네 영상을 획득하는 데 있어서 초당 프레임 횟수를 변화함에 따라 흡수선량과 획득 영상의 화질의 추이를 살펴보는 것을 목적으로 한다. 또, FOV 확대와 Live Zoom이라는 두 가지 확대 모드에 따른 변화도 고찰 대상으로 한다. 인체모형 팬텀을 심장 혈관 조영장치 위에서 초당 프레임 횟수를 7.5, 15, 30 f/s로 설정하고 두 가지 확대 모드에 대하여 각각 5회씩 촬영하였다. 선량의 척도로서는 흡수선량과 에어 커머가 사용되었고, 화질 평가의 척도로는 잡음의 세기로서의 표준 편차(SD), 신호 대 잡음비(SNR)와 대조도 대 잡음비(CNR) 등을 활용하였다. 초당 프레임 횟수가 30부터 15, 7.5 f/s로 감소되었을 때, DAP와 에어 커머는 동일한 비율로 감소하였으나, 화질의 척도인 SD, SNR과 CNR은 거의 변화가 없었다. 확대 모드에의 의존도에 관해서는, Live Zoom이 FOV 확대와 비교하였을 때, DAP, 에어 커머와 SD에 대해서는 통계적 의미 있는 차이를 보이지 않았으나, SNR과 CNR에 있어서는 통계적 유의미한 개선을 보였다. 이러한 실험 결과에 의하여, 초당 프레임 횟수는 화질의 열화 없이 되도록 낮게 설정하는 것이 가능하며, 확대 모드도 추가적인 선량 없이 실시간 확대가 가능한 Live Zoom 모드를 적극적으로 활용 가능하며 이는 화질의 여러 척도의 저하를 가져오지 않음을 알 수 있었다.

• IEIE Transactions on Smart Processing and Computing
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• 제1권3호
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• pp.152-160
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• 2012

This paper proposes a frame-level rate control algorithm for low delay video applications to reduce the fluctuations in the bitrate. The proposed algorithm minimizes the bitrate fluctuations in two ways with minimal coding loss. First, the proposed rate control applies R-Q model to all frames including the first frame of every group of pictures (GOP) except for the first one of a sequence. Conventional rate control algorithms do not use any R-Q models for the first frame of each GOP and do not estimate the generated-bit. An unexpected output rate result from the first frame affects the remainder of the pictures in the rate control. Second, a rate-distortion (R-D) cost is calculated regardless of the hierarchical coding structure for low bitrate fluctuations because the hierarchical coding structure controls the output bitrate in rate distortion optimization (RDO) process. The experimental results show that the average variance of per-frame bits with the proposed algorithm can reduce by approximately 33.8% with a delta peak signal-to-noise ratio (PSNR) degradation of 1.4dB for a "low-delay B" coding structure and by approximately 35.7% with a delta-PSNR degradation of 1.3dB for a "low-delay P" coding structure, compared to HM 8.0 rate control.

• Journal of the Optical Society of Korea
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• 제17권6호
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• pp.513-517
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• 2013

Recently, maskless lithography (ML) systems have become popular in digital manufacturing technologies. To achieve high-throughput manufacturing processes, digital micromirror devices (DMD) in ML systems must be driven to their operational limits, often in harsh conditions. We propose an instrument and algorithm to detect DMD malfunctions to ensure perfect mask image transfer to the photoresist in ML systems. DMD malfunctions are caused by either bad DMD pixels or data transfer errors. We detect bad DMD pixels with $20{\times}20$ pixel by white and black image tests. To analyze data transfer errors at high frame rates, we monitor changes in the frame rate of a target DMD pixel driven by the input data with a set frame rate of up to 28000 frames per second (fps). For our data transfer error detection method, we verified that there are no data transfer errors in the test by confirming the agreement between the input frame rate and the output frame rate within the measurement accuracy of 1 fps.

• 대한전자공학회논문지SP
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• 제47권2호
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• pp.33-44
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• 2010

본 논문에서는 로봇 시각 처리 활용을 위한 실시간 얼굴 검출 하드웨어 구조를 제안한다. 제안한 구조는 조명 변화에 강인하고 초당 60 프레임 이상의 속도로 처리된다. 조명 변화에 강인한 얼굴 특성 추출을 위해 MCT(Modified Census Transform) 변환을 이용하였다. 그리고 AdaBoost 알고리즘은 얼굴 특징 데이터의 학습 및 생성을 하며, 이 생성된 학습 데이터를 이용해 얼굴 검출을 하게 된다. 본 논문에서는 메모리 인터페이스부, 이미지 크기 조정부, MCT 생성부, 후보 얼굴 검출부, 신뢰도 비교부, 좌표 재조정부, 데이터 그룹화부, 검출 결과 표시부로 구성된 얼굴 검출 하드웨어 구조 및 Xilinx사의 Virtex5 LX330 FPGA를 이용한 하드웨어 구현 검증 결과에 대해 설명한다. 카메라로 부터 입력받은 이미지를 이용해 검증한 결과로 초당 최대 149프레임의 속도로 한 프레엠 당 최대 32개 얼굴을 검출함을 확인하였다.

• 소성∙가공
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• 제28권6호
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• pp.368-374
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• 2019

The past recent years have seen an increasing use of high-strength steel sheets in the automotive industry. However, the formability and damage prediction of these materials requires accurate acquisition of necking and fracture strains. Digital image correlation (DIC) is used to accurately capture the necking and fracture strains during testing. The fact that single time points of capturing vary with frame rate makes the need for an investigation necessary. For the high-strength steel DP980, the frame-rate dependences of the final necking and fracture strains values are analyzed here. To eliminate the influence of gauge length, the strains were measured locally by DIC. Results for three specimen shapes obtained with frame rates of 1 and 900 fps (frames per second) were considered and based on them, triaxiality failure diagrams (TFD) are established. It was observed that after diffuse necking, the deformation path departed from the initially linear one, and the stress triaxiality grew with ongoing deformation. It was further revealed that the frame rate-dependence of the necking strain was rather low (< 2%), whereas the fracture strain could be underestimated by up to 8% when the lower frame rate of 1 fps was used (compared with 900 fps). In this study, this issue is investigated while taking into consideration the three different triaxialities. These results demonstrate the importance of choosing an appropriate frame rate for the determination of necking and fracture strains in particular.

• 전자공학회논문지C
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• 제35C권5호
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• pp.25-32
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• 1998

In this paper, SA (shape adaptive)-DCT is implemented using a datapath with 4 MACs (multiplication & accumulator). DCT is a well-known bottleneck of real-time video compression using MPEG-like schemes. High-speed pipelined MACs presented here implement real-time DCT. A datapath in this paper executes DCT/IDCT algorithms for QCIF 15fps(frame per second), maximum rate of VLBV(very low bitrte video) in MPEG-4. A 32bit accumulator in a MAC prevents distortion caused by fixed-point process. It can be applied to various operations such as ME (motion estimation) and MC(motion compensation) with a absolutor and a halfer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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• pp.235-238
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• 2002

This paper presents a way of a novel FPGA implementation of DCT. It shows how to limit the required bits on each DCT processing step, instead of implementing high-cost 64-bit floating-point arithmetic of IEEE Std 754-1985 on FPGA. ID-DCT implementation has been done which operates at 30 frame per second with 1920${\times}$1080 resolution.

• 한국정보통신학회논문지
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• 제12권6호
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• pp.1064-1069
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• 2008

본 논문은 인터프레임 확률분포에 의한 비디오 감시 시스템 설계 구현에 관한 것이다. 시스템은 비디오 분석 알고리즘과 표준 JPEG 압축 알고리즘을 처리하기 위해 고성능 DSP 프로세서 기반으로 구현된다. 비디오 분석은 가중치, 평균, 분산의 3변량정규분포에 의한 인터프레임 확률분포 분석을 이용하여 특정 영역에 물체를 검출하는 알고리즘을 사용한다. 실험 결과, 시스템 처리시간이 D1$(720{\times}480)$ 영상 프레임 당 85ms 소요되었고 초당 12프레임 정도 처리한다. 규칙에 따른 특정영역 물체감시는 움직임 빠르지 않는 물체에 대해 100% 검출되었다.