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Design and Implementation of Real-time High Performance Face Detection Engine  

Han, Dong-Il (Dept. of Computer Engineering, Sejong University)
Cho, Hyun-Jong (Dept. of Computer Engineering, Sejong University)
Choi, Jong-Ho (Dept. of Computer Engineering, Sejong University)
Cho, Jae-Il (Robot Research Department, ETRI)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.47, no.2, 2010 , pp. 33-44 More about this Journal
Abstract
This paper propose the structure of real-time face detection hardware architecture for robot vision processing applications. The proposed architecture is robust against illumination changes and operates at no less than 60 frames per second. It uses Modified Census Transform to obtain face characteristics robust against illumination changes. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data, and finally detected the face using this data. This paper describes the face detection hardware structure composed of Memory Interface, Image Scaler, MCT Generator, Candidate Detector, Confidence Comparator, Position Resizer, Data Grouper, and Detected Result Display, and verification Result of Hardware Implementation with using Virtex5 LX330 FPGA of Xilinx. Verification result with using the images from a camera showed that maximum 32 faces per one frame can be detected at the speed of maximum 149 frame per second.
Keywords
Modified Census Transform; Adaboost Algorithm; Face Detection; Real-Time; FPGA Implementation; Hardware Design;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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