• Title/Summary/Keyword: frame memory

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ASIC Design of Frame Sync Algorithm Using Memory for Wireless ATM (무선 ATM망에서 메모리를 이용한 프레임 동기 알고리즘의 ASIC 설계)

  • 황상철;김종원
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.82-85
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    • 1998
  • Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

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A Study on Effective Optimization by Comparison with FMQ of Real-time Rendering for Variable Surface Formats (다양한 텍스처 형식에 따른 실시간 렌더링의 FMQ 비교를 통한 효과적인 최적화(Optimization) 기법에 관한 연구)

  • Chae Heon-Joo;Ryu Seuc-Ho;Kyung Byung-Pyo
    • Proceedings of the Korea Contents Association Conference
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    • 2005.11a
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    • pp.13-18
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    • 2005
  • Textures used in the game and VR environments with real-time rendering technology have different results according to used texture format supported video card. We propose some ideas for the texture using method by comparison with Frame Rate, Video Memory, and Quality.

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Parallel Implementation of Nonlinear Analysis Program of PSC Frame Using MPI (MPI를 이용한 PSC 프레임 비선형해석 프로그램의 병렬화)

  • 이재석;최규천
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 2001.04a
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    • pp.61-68
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    • 2001
  • A parallel nonlinear analysis program of prestressed concrete frame is migrated on a PC cluster system and a massively parallel processing system, CRAY T3E system, using MPI. The PC cluster system is configured with Pentium Ⅲ class PCs and fast ethernet. The CRAY T3E system is composed of a set of nodes each containing one Processing Element (PE), a memory subsystem and its distributed memory interconnect network. Parallel computing algorithms are implemented on element-wise processing parts including the calculation of stiffness matrix, element stresses and determination of material states, check of material failure and calculation of unbalanced loads. Parallel performance of the migrated program is evaluated through typical numerical examples.

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Numerical Study on the Local Motion of an A-frame for Deep Sea ROV Mother Ship in Irregular Waves (심해잠수정 모선의 A-프레임 시간영역 국부운동해석)

  • Hong, Do-Chun;Lee, Pan-Mook
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2003.05a
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    • pp.105-108
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    • 2003
  • The local motion at the top of an A-frame fixed on a research vessel for deep sea ROV floating in irregular waves is studied in the time-domain. The motion is analyzed in the time-domain using the convolution integral of the radiation forces. The memory effect functions and infinite frequency added masses are obtained from the solution of the three dimensional improved Green integral equation in the frequency domain by making use of the Fourier transformation.

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Seismic response of RC structures rehabilitated with SMA under near-field earthquakes

  • Shiravand, M.R.;Khorrami Nejad, A.;Bayanifar, M.H.
    • Structural Engineering and Mechanics
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    • v.63 no.4
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    • pp.497-507
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    • 2017
  • During recent earthquakes, a significant number of concrete structures suffered extensive damage. Conventional reinforced concrete structures are designed for life-time safety that may see permanent inelastic deformation after severe earthquakes. Hence, there is a need to utilize adequate materials that have the ability to tolerate large deformation and get back to their original shape. Super-elastic shape memory alloy (SMA) is a smart material with unique properties, such as the ability to regain undeformed shape by unloading or heating. In this research, four different stories (three, five, seven and nine) of reinforced concrete (RC) buildings have been studied and subjected to near-field ground motions. For each building, two different types of reinforcement detailing are considered, including (1) conventional steel reinforcement (RC frame) and (2) steel-SMA reinforcement (SMA RC frame), with SMA bars being used at plastic zones of beams and steel bars in other regions. Nonlinear time history analyses have been performed by "SeismoStruct" finite element software. The results indicate that the application of SMA materials in plastic hinge regions of the beams lead to reduction of the residual displacement and consequently post-earthquake repairs. In general, it can be said that shape memory alloy materials reduce structural damage and retrofit costs.

Seismic Performance of an Inverted V-type Eccentrically Braced Steel Frames with Slit Dampers Using Shape Memory Alloy (형상기억합금을 이용한 슬릿댐퍼 적용 역V형 편심가새골조의 내진 성능)

  • Jang, Han Ryul;Kim, Joo-Woo
    • Journal of Korean Association for Spatial Structures
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    • v.22 no.4
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    • pp.39-48
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    • 2022
  • The energy dissipation of inverted V-type eccentric steel braced frames can be achieved through the yielding of a slit link, through yielding of a number of strips between slits when the frame is subjected to inelastic cyclic deformation. On the other hand, the development of seismic resistance system without residual deformation is obtained by applying the superelasdtic shape memory alloy (SMA) material into the brace and link elements. This paper presents results from a systematic three-dimensional nonlinear finite element analysis on the structural behavior of the eccentric bracing systems subjected to cyclic loadings. A wide scope of structural behaviors explains the horizontal stiffness, hysteretic behaviors, and failure modes of the recentering eccentric bracing system. The accurate results presented here serve as benchmark data for comparison with results obtained using modern experimental testing and alternative theoretical approaches.

The design of high profile H.264 intra frame encoder (H.264 하이프로파일 인트라 프레임 부호화기 설계)

  • Suh, Ki-Bum
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2285-2291
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    • 2011
  • In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

Vision-based support in the characterization of superelastic U-shaped SMA elements

  • Casciati, F.;Casciati, S.;Colnaghi, A.;Faravelli, L.;Rosadini, L.;Zhu, S.
    • Smart Structures and Systems
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    • v.24 no.5
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    • pp.641-648
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    • 2019
  • The authors investigate the feasibility of applying a vision-based displacement-measurement technique in the characterization of a SMA damper recently introduced in the literature. The experimental campaign tests a steel frame on a uni-axial shaking table driven by sinusoidal signals in the frequency range from 1Hz to 5Hz. Three different cameras are used to collect the images, namely an industrial camera and two commercial smartphones. The achieved results are compared. The camera showing the better performance is then used to test the same frame after its base isolation. U-shaped, shape-memory-alloy (SMA) elements are installed as dampers at the isolation level. The accelerations of the shaking table and those of the frame basement are measured by accelerometers. A system of markers is glued on these system components, as well as along the U-shaped elements serving as dampers. The different phases of the test are discussed, in the attempt to obtain as much possible information on the behavior of the SMA elements. Several tests were carried out until the thinner U-shaped element went to failure.

Study on the Mechanical Properties and Thermal Conductive Properties of Cu/STS/Cu Clad Metal for LED/semiconductor Package Device Lead Frame (LED 및 반도체 소자 리드프레임 패키징용 Cu/STS/Cu 클래드메탈의 기계적/열전도/전기적 특성연구)

  • Lee, Chang-Hun;Kim, Ki-Chul;Kim, Young-Sung
    • Journal of Welding and Joining
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    • v.30 no.3
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    • pp.32-37
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    • 2012
  • Lead frame which has a high thermal conductivity and high mechanical strength is one of core technology for ultra-thin electronics such as LED lead frames, memory devices of semiconductors, smart phone, PDA, tablet PC, notebook PC etc. In this paper, we fabricated a Cu/STS/Cu 3-layered clad metal for lead frame packaging materials and characterized the mechanical properties and thermal conductive properties of the clad metal lead frame material. The clad metal lead frame material has a comparable thermal conductivity to typical copper alloy lead frame materials and has a reinforced mechanical tensile strength by 1.6 times to typical pure copper lead frame materials. The thermal conductivity and mechanical tensile strength of the Cu/STS/Cu clad metal are 284.35 W/m K and $52.78kg/mm^2$, respectively.

Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec

  • Kim, Sunwoong;Jang, Ji Hun;Lee, Hyuk-Jae;Rhee, Chae Eun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.446-457
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    • 2017
  • In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.